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69 results for “Hardware implementation”
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Research ArticleOpen accessIn the abstractReconfigurable Hardware Architecture for Network Intrusion Detection SystemA. Kaleel Rahuman, G. AthishaIntrusion rule processing in reconfigurable hardware enables intrusion detection and prevention. The use of reconfigurable hardware for network security applications has great strides as Field Programmable Gate Array (FPGA) devices have provided larger and faster resources. This proposes architecture called “BV-TCAM” is presented, which is implemented for an FPGA-based Network Intrusion Detection Systems (NIDS). The BV-TCAM architecture combines the Ternary … …American Journal of Applied Sciences, Vol. 9, Issue 10 · 16 Aug 2012 · 6,985 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. NirmalKumar, T. MayilsamyProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 21 Jul 2012 · 7,361 accessesView PDFCite
Research ArticleOpen accessIn the abstractComparative Study of Performance in Cryptography Algorithms (Blowfish and Skipjack)Ali Ahmad Milad, Hjh Zaiton Muda, Zul Azri Bin Muhamad Noh, Mustafa Almahdi AlgaetProblem statement: The main goal guiding the design of any encryption algorithm needs to be secured against unauthorized attacks. For all applied applications, performance and the cost of implementations are also important concerns. A data encryption algorithm would not be of much use if it is secure enough but slow in performance because it is a common repetition to embed … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jul 2012 · 8,021 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Field Programmable Gate Array Based Emulators for Motor Control ApplicationsAhmed Ben Achballah, Slim Ben Othman, Slim Ben SaoudProblem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 12 Jun 2012 · 8,726 accessesView PDFCite
Research ArticleOpen accessIn the abstractBuffer Pocketing and Pre-Checking on Buffer UtilizationK. Saravanan, R. M. SureshProblem statement: In this study, the paper proposes the development of Effective Buffer Utilization on Adaptive Router with Buffer Pocketing and Pre-Buffer Checking Technique. Network-on-Chip could be prepared more capable by tricky faster routers. By using improved buffers, superior number of ports and channels, adaptive routing, all of which acquire key of overheads in hardware costs. Approach: This technique will … …Journal of Computer Science, Vol. 8, Issue 6 · 23 Apr 2012 · 6,914 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. Nirmal KumarProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testing the architectures which need … …Journal of Computer Science, Vol. 8, Issue 6 · 13 Mar 2012 · 7,769 accessesView PDFCite
Research ArticleOpen accessIn the abstractDynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive ImplementationHedi Abdelkrim, Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben SaoudProblem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using … …American Journal of Engineering and Applied Sciences, Vol. 5, Issue 1 · 18 Feb 2012 · 8,983 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,680 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Single Core Hardware Module of a Data Compression Scheme Using Prediction by Partial Matching TechniqueJubayer Jalil, Md. Mamun, Mohd. Marufuzzaman, Hafizah HusainProblem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,258 accessesView PDFCite
Research ArticleOpen accessIn the abstractSubway Train Braking System: A Fuzzy Based Hardware ApproachMamun Bin Ibne Reaz, Jubayer Jalil, Hafizah Husain, Badariah BaisProblem statement: Automated subway train-braking system require perfection, efficiency and fast response. In order to cope with this concerns, an appropriate algorithm need to be developed which need to be implemented in hardware for faster response. Approach: In this research, the FPGA realization of fuzzy based subway train braking system has been presented on an Alter FLEX10K device to provide … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 7,179 accessesView PDFCite