A Single Core Hardware Module of a Data Compression Scheme Using Prediction by Partial Matching Technique

Problem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original and the decompressed data be identical, or where deviations from the original data could be deleterious. Approach: Prediction by Partial Matching (PPM) data compression technique had utmost performance standard and capable of very good compression on a variety of data. In this research, we had introduced PPM technique to compress the data and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The PPM algorithm was modeled using the hardware description language VHDL. Results: Functional simulations were commenced to verify the functionality of the system with both 16-bit input and 32-bit input. The FPGA utilized 1164 logic cells with a maximum system frequency of 95.3MHz on Altera FLEX10K. Conclusion: The proposed approach is computationally simple, accurate and exhibits a good balance of flexibility, speed, size and design cycle time.