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69 results for “Hardware implementation”
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Research ArticleOpen accessPhrase in the titleDigital Hardware Implementation of a Neural System Used for Nonlinear Adaptive PredictionHassène Faiedh, Chokri Souani, Kholdoun Torki, Kamel BesbesNeural networks have been widely used for many applications in digital communications. They are able to give solutions to complex problems due to their nonlinear processing and their learning and generalization. Neural networks are one of the key technologies for the communication domain and accordingly a special effort may be expected to be paid to real time hardware implementation issues. … …Journal of Computer Science, Vol. 2, Issue 4 · 30 Apr 2006 · 6,767 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleQuantization and Pipelined Hardware Implementation of Deep Neural Network ModelsEl Hadrami Cheikh Tourad, Mohsine EleuldjInrecent years, Deep Neural Networks (DNNs) have garnered much interest due toadvances in computational power and data availability. Indeed, DNNs presents a considerable advantage in several challenges, suchas classification problems and video analysis. Although, such accomplishmentleads to significantly increasing energy demands, computational expenses, andmemory capacity. In addition, current efficient DNNs may have more complex andextensive structures. As a result, implementing … …Journal of Computer Science, Vol. 18, Issue 11 · 26 Oct 2022 · 5,707 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleHardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA DevicesMuhammad H. RaisProblem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,338 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,520 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,447 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleLow Power Hardware Implementation of High Speed FFT CoreM. Kannan, S. K. SrivatsaApplications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift … …Journal of Computer Science, Vol. 3, Issue 6 · 30 Jun 2007 · 7,231 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleEfficient Implementation of Stochastic Computing Based Deep Neural Network on Low Cost Hardware with Saturation ArithmeticSunny Bodiwala, Nirali NanavatiThis study presents an efficient and rapid implementation of Stochastic Computing (SC) based Deep Neural Network (DNN) on a low-cost hardware platform. The proposed technique uses bipolar signal encoding in stochastic computing which relatively gives low hardware footprint compared to binary computing. Thereinafter, stochastic max function is presented and subsequently used to approximate the hyperbolic tangent activation function in SC. … …Journal of Computer Science, Vol. 16, Issue 11 · 17 Nov 2020 · 6,879 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleOptimised Implementation of Dense Stereo Correspondence for Resource Limited HardwareDeepambika Vadekkettathu Anirudhan, Malangai Abdul RahimanComputer stereo vision is a passive sensing technique that helps to recover 3D information of an environment from 2D images. The stereo correspondence is a challenging task that finds out matching pixels between the stereo image pair based on Lambertian criteria and its result is a disparity space image. The depth of the objects from the camera can be calculated … …Journal of Computer Science, Vol. 14, Issue 10 · 18 Oct 2018 · 7,332 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleSoftware Defined Radio Implementation of a QPSK Modulator/Demodulator in an Extensive Hardware Platform Based on FPGAs Xilinx ZYNQSérgio Bimbi Junior, Vitor Chaves de Oliveira, Gunnar Bedicks JuniorSoftware Defined Radio (SDR) technology enables wireless devices deployment with support to multiple interfaces in modulation formats and it has gained importance due to the current wireless standards proliferation. In order to activate these functionalities it is necessary to apply SDR inside a reconfigurable hardware such as the Field Programmable Gate Array (FPGA). In this study, design procedures developments are … …Journal of Computer Science, Vol. 11, Issue 4 · 2 Jun 2015 · 8,818 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDESIGN IMPLEMENTATION AND HARDWARE STRUCTURE FOR IMAGE ENHANCEMENT AND SURFACE ROUGHNESS WITH FEATURE EXTRACTION USING DISCRETE WAVELET TRANSFORMSyed Jahangir Badashah, P. SubbaiahIn this study we provide the implementation design and hardware structure for the architecture proposed in the previous paper &#34Image Enhancement and Surface Roughness with Feature Extraction using DWT&#34 IEEE DoI/10.1049/cp.2011.0464. The proposed architecture has been implemented in Microwind and Tanner for power analysis and characteristic study. The result shows very low power consumption than the existing method for a … …Journal of Computer Science, Vol. 10, Issue 2 · 20 Nov 2013 · 6,784 accessesView PDFCite