Research ArticleOpen accessEvery word in the titleERROR DETECTION SCHEMES FOR FINITE FIELD MULTIPLIERSB. Sargunam, R. DhanasekaranFinite field multipliers are widely used in the field of cryptography for the purpose of scalar multiplication. The outputs of the finite field multipliers may consist of errors due to certain natural radiations which further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for … …American Journal of Applied Sciences, Vol. 11, Issue 1 · 11 Dec 2013 · 6,913 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleBraun's Multipliers: Spartan-3AN based Design and ImplementationMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The … …Journal of Computer Science, Vol. 7, Issue 11 · 18 Aug 2011 · 6,909 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleMunicipalities as Sports MultipliersRudolf LeberProblem statement: It is generally agreed that sports must be made available for children and young people. The children and youth of urban areas should be encouraged to form meaningful sporting activities under the guidance of sport teachers. Approach: Based on a study of the leisure activities of the Vienna children and young people through the city of Vienna, the … …Journal of Social Sciences, Vol. 8, Issue 1 · 4 Nov 2011 · 7,852 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,612 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleField Programmable Gate Arrays Based Realization of Truncated MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 6,694 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleSpartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay StudyMohammed H. Al MijalliProblem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be … …American Journal of Applied Sciences, Vol. 8, Issue 6 · 13 Jun 2011 · 6,428 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley MultipliersMuhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, Fahad K. Al-HusseinProblem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 2 · 30 Jun 2010 · 8,123 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Novel Methodology for Designing Radix-2n Serial-Serial MultipliersAbdurazzag Sulaiman AlmiladiProblem statement: The fast growth and increase in complexity of digital and image processing systems necessitate the migration from ad hoc design methods to methodological ones. Methodologies will certainly ease the trade off selection for those systems and shortens the design time. To increase those gained values and expand the searching space more appropriate methodologies need to be developed. Approach: … …Journal of Computer Science, Vol. 6, Issue 4 · 30 Apr 2010 · 6,922 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA DevicesMuhammad H. RaisProblem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,334 accessesView PDFCite