Sign inSubmit
Tips: “quotes” for a phrase · author:Lee · a DOI goes straight to its article

45 articles for “CMOS”
Set a search alert
Research ArticleOpen accessEvery word in the titleA Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection RatioIsmail Nabhan, Moussa AbdallahProblem statement: High speed operational amplifier is always an on-going research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0.5 μm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure stability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,237 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of a Current Sensor for IDDQ Testing of CMOS ICMohd Liakot Ali, Nurul Huda KhamisThis study presents the design of an off-chip current sensor for IDDQ testing of CMOS (Complementary Metal-oxide Semiconductor) ICs (integrated circuit). It provides a linear voltage signal of IDDQ current with a conversion factor of 5 mV/μA without any amplification. A voltage-controlled switch is used to bypass the transient current peaks. It has also been shown that the sensor is … …American Journal of Applied Sciences, Vol. 2, Issue 3 · 31 Mar 2005 · 6,834 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS TechnologySiva Kumar Palaniappan, Tun Zainal Azni ZulkifliThis paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes … …American Journal of Applied Sciences, Vol. 4, Issue 8 · 31 Aug 2007 · 7,164 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCSBakoune Pierre Hypolite, Wembe Tafo Evariste, Moukengue Imano AdolpheThis paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results … …American Journal of Engineering and Applied Sciences, Vol. 12, Issue 2 · 6 May 2019 · 7,671 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel High-Speed 54⨯54 bit MultiplierPouya Asadi, Keivan NaviA new 54⨯54-bit multiplier using high-speed carry-lookahead adder has been fabricated by CMOS technology. This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has … …American Journal of Applied Sciences, Vol. 4, Issue 9 · 30 Sep 2007 · 7,083 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of a Low Power and High Speed Comparator using MUX based Full Adder Cell for Mobile CommunicationsG. Ramana Murthy, Ajay Kumar Singh, P. Velraj Kumar, Tan Wee Xin WilsonThis paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate … …American Journal of Applied Sciences, Vol. 14, Issue 1 · 16 Jan 2017 · 8,251 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA DC-DC Circuit Using Boost Converter for Low Voltage Energy Harvesting ApplicationNurul Arfah Che Mustapha, A.H.M. Zahirul Alam, Sheroz Khan, Amelia Wong AzmanA DC-DC step-up voltage converter is designed to convert a very low voltage supply, 35 mV such as from the thermal energy source from body heat. The converter can generate an output voltage up to 210 mV, approximately six imes its initial input voltage over a frequency of 36 GHz. The effect of switching transistors, inductor current, rise and fall … …American Journal of Applied Sciences, Vol. 12, Issue 4 · 9 Jun 2015 · 6,980 accessesView PDFCite
Research ArticleOpen accessIn the keywordsVLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless ReceiversRozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman et al.Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,815 accessesView PDFCite
Research ArticleOpen accessIn the keywordsOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,924 accessesView PDFCite
Research ArticleOpen accessIn the keywordsSource Couple Logic (SCL): Theory and Physical DesignMohamed Azaga, Masuri OthmanThis study describes and presents the analysis for the Source-Coupled Logic (SCL) inverter as will as the effect of submicron layout parasitics. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics and the effect of noise margin. The inverter gate delay model is … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 1 · 31 Mar 2008 · 7,466 accessesView PDFCite