A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS
Bakoune Pierre Hypolite1, Wembe Tafo Evariste1 & Moukengue Imano Adolphe1 Show affiliations
- University of Douala, Cameroon
American Journal of Engineering and Applied Sciences, Volume 12, Issue 2, pp. 156–165 · doi.org/10.3844/ajeassp.2019.156.165
Abstract
This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GHZ. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.
Licence and reuse
Open access. This article is licensed under a Creative Commons Attribution 3.0 Licence (CC BY 3.0), as printed on the article, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original authors and the source. No permission is needed.
How to reuse this articleResponses (0)
About this article
Hypolite, B. P., Evariste, W. T. & Adolphe, M. I. (2019). A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS. American Journal of Engineering and Applied Sciences, 12(2), 156–165. https://doi.org/10.3844/ajeassp.2019.156.165
- Licence
- CC BY 3.0
- Issue
- Volume 12, Issue 2
- Policies
- Editorial independenceUse of generative AIData availabilityAppeals and complaints
- Version
- Version of record