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8 results for “Boolean circuit”
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Research ArticleOpen accessEvery word in the titleSingle Stuck-At Fault Diagnosing Circuit of Reed-Muller Canonical Exclusive-Or Sum of Product Boolean ExpressionsP. N. Neelakantan, A. E. JeyakumarA testable design with a universal test set for single stuck-at zero and stuck-at one faults of Reed-Muller canonical form of Exclusive-OR sum of product logic expressions is proposed. The test circuit detects almost all the single stuck-at faults and needs only simple modifications for variations in the circuit under test. The number of test vectors is also quite small … …Journal of Computer Science, Vol. 2, Issue 7 · 31 Jul 2006 · 6,587 accessesView PDFCite
Research ArticleOpen accessIn the keywordsSimulation of Parallel Logical Operations with Biomolecular ComputingMahnaz Kadkhoda, Ali A. PouyanBiomolecular computing is the computational method that uses the potential of DNA as a parallel computing device. DNA computing can be used to solve NP-complete problems. An appropriate application of DNA computation is large-scale evaluation of parallel computation models such as Boolean Circuits. In this study, we present a molecular-based algorithm for evaluation of Nand-based Boolean Circuits. The contribution of … …American Journal of Applied Sciences, Vol. 5, Issue 12 · 31 Dec 2008 · 6,687 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of a Low Power and High Speed Comparator using MUX based Full Adder Cell for Mobile CommunicationsG. Ramana Murthy, Ajay Kumar Singh, P. Velraj Kumar, Tan Wee Xin WilsonThis paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate … …American Journal of Applied Sciences, Vol. 14, Issue 1 · 16 Jan 2017 · 8,251 accessesView PDFCite
Research ArticleOpen accessIn the abstractSingle Core Hardware Module to Implement Boolean Function Classification TechniquesMohd. Marufuzzaman, Md. Mamun, Fazidah Hanim Hashim, Labonnah F. RahmanProblem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,408 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Fault Tolerant Reversible Gate For Nanotechnology Based SystemsMajid Haghparast, Keivan NaviThis paper proposes a novel reversible logic gate, NFT. It is a parity preserving reversible logic gate, that is, the parity of the outputs matches that of the inputs. We demonstrate that the NFT gate can implement all Boolean functions. It renders a wide class of circuit faults readily detectable at the circuit's outputs. The proposed parity preserving reversible gate, … …American Journal of Applied Sciences, Vol. 5, Issue 5 · 31 May 2008 · 7,904 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Reversible BCD Adder For Nanotechnology Based SystemsMajid Haghparast, Keivan NaviThis paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as &#34Copying Circuit&#34 to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all … …American Journal of Applied Sciences, Vol. 5, Issue 3 · 31 Mar 2008 · 10,135 accessesView PDFCite
Research ArticleOpen accessIn the abstractEmpirical Analysis and Mathematical Representation of the Path Length Complexity in Binary Decision DiagramsA. Assi, P. W.C. Prasad, B. Mills, A. ElchouemiInformation about the distribution of path-lengths in a Binary Decision Diagrams (BDDs) representing Boolean functions is useful in determining the speed of hardware and software implementations of the circuit represented by these Boolean functions. This study presents expressions produced from an empirical analysis of a representative collection of Boolean functions. The Average Path Length (APL) and the Shortest Path Length … …Journal of Computer Science, Vol. 2, Issue 3 · 31 Mar 2006 · 6,814 accessesView PDFCite
Research ArticleOpen accessIn the abstractBDD Path Length Minimization Based on Initial Variable OrderingP. W.C. Prasad, M. Raseen, A. Assi, S. M.N.A. SenanayakeA large variety of problems in digital system design, combinational optimization and verification can be formulated in terms of operations performed on Boolean functions. The time complexity of Binary Decision Diagram (BDD) representing a Boolean function is directly related to the path length of that BDD. In this paper we present a method to generate a BDD with minimum path … …Journal of Computer Science, Vol. 1, Issue 4 · 31 Dec 2005 · 6,504 accessesView PDFCite