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54 articles for “multiplier”
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Research ArticleOpen accessEvery word in the titlePerformance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDLHasan Krad, Aws Y. Al-TaieThis study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study's main focus is on the speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a … …Journal of Computer Science, Vol. 4, Issue 4 · 30 Apr 2008 · 7,385 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Bipolar Cockcroft-Walton Voltage Multiplier for Gas LasersShahid Iqbal, Rosli BesarA bipolar Cockcroft-Walton voltage multiplier (CWVM) is proposed as an attractive alternative to the symmetrical Cockcroft-Walton voltage multiplier for continuous wave gas lasers (e.g. carbon dioxide gas laser). The proposed CWVM formed by combining positive and negative voltage multipliers consisting of equal number of stages and driving in parallel by an ac voltage source. The proposed voltage multiplier needs only … …American Journal of Applied Sciences, Vol. 4, Issue 10 · 31 Oct 2007 · 8,270 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleField Programmable Gate Arrays Based Realization of Truncated MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 6,694 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley MultipliersMuhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, Fahad K. Al-HusseinProblem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 2 · 30 Jun 2010 · 8,123 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Novel Approach for Testing Stability of 1-D Recursive Digital Filters Based on Lagrange MultipliersK. R. Santhi, N. Gangatharan, M. PonnavaikkoDigital filters have found their way into many products from every day consumer items such as mobile phones to advanced maritime and military communications and avionics systems. Design of digital filters faces two fundamental problems, their stability and synthesis. Recursive filters have more stability problems than nonrecursive filters. Stability of a filter can be determined by the location of the … …American Journal of Applied Sciences, Vol. 5, Issue 5 · 31 May 2008 · 6,484 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleERROR DETECTION SCHEMES FOR FINITE FIELD MULTIPLIERSB. Sargunam, R. DhanasekaranFinite field multipliers are widely used in the field of cryptography for the purpose of scalar multiplication. The outputs of the finite field multipliers may consist of errors due to certain natural radiations which further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for … …American Journal of Applied Sciences, Vol. 11, Issue 1 · 11 Dec 2013 · 6,913 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleMunicipalities as Sports MultipliersRudolf LeberProblem statement: It is generally agreed that sports must be made available for children and young people. The children and youth of urban areas should be encouraged to form meaningful sporting activities under the guidance of sport teachers. Approach: Based on a study of the leisure activities of the Vienna children and young people through the city of Vienna, the … …Journal of Social Sciences, Vol. 8, Issue 1 · 4 Nov 2011 · 7,852 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleAREA EFFICIENT DISTRIBUTED ARITHMETIC DISCRETE COSINE TRANSFORM USING MODIFIED WALLACE TREE MULTIPLIERR. P. Meenaakshi Sundari, R. Anita, V. VenkateshwaranIn this study by using the modified Wallace tree multiplier, an error compensated adder tree is constructed in order to round off truncation errors and to obtain high through put discrete cosine transform design. Peak Signal to Noise Ratio (PSNR) is met efficiently since modified Wallace Tree method is an efficient, hardware implementable digital circuit that multiplies two integers resulting … …American Journal of Applied Sciences, Vol. 11, Issue 2 · 19 Dec 2013 · 7,331 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Analog Multiplier Using MifgmosK. Duraisamy, U. RagavendranA novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is … …Journal of Computer Science, Vol. 9, Issue 4 · 14 May 2013 · 6,343 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite