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133 results for “Architectures”
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Research ArticleOpen accessIn the abstractNew Constructive Neural Network Architecture for Pattern ClassificationS. S. Sridhar, M. PonnavaikkoProblem statement: Constructive neural network learning algorithms provide optimal ways to determine the architecture of a multi layer perceptron network along with learning algorithms for determining appropriate weights for pattern classification problems. These algorithms initially start with small network and dynamically allow the network to grow by adding and training neurons as needed until a satisfactory solution is found. The … …Journal of Computer Science, Vol. 5, Issue 11 · 30 Nov 2009 · 6,565 accessesView PDFCite
Research ArticleOpen accessIn the abstractInverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHzMahmoud AbdellaouiProblem statement: In this study and in consequence of the restricted performance of the multi standard wireless receiver utilizing the classical architectures, we proposed and presented a new architecture of multi band wireless receiver based on an Inverse Sine Phase Detector Phase Locked Loop (ISPDPLL) associated with modified multi band LC quadrature Voltage Controlled Oscillator (VCO), supporting GSM/DCS/DECT/Bluetooth/WiMax systems. Approach: … …American Journal of Engineering and Applied Sciences, Vol. 2, Issue 2 · 30 Jun 2009 · 8,251 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Light-Weight Service Discovery Protocol for Ad Hoc NetworksRanwa Al Mallah, Alejandro QuinteroProblem statement: In mobile ad hoc networks devices do not rely on a fixed infrastructure and thus have to be self-organizing. This gives rise to various challenges to network applications. Existing service discovery protocols fall short of accommodating the complexities of the ad-hoc environment. However, the performance of distributed service discovery architectures that rely on a virtual backbone for locating … …Journal of Computer Science, Vol. 5, Issue 4 · 30 Apr 2009 · 7,336 accessesView PDFCite
Research ArticleOpen accessIn the abstractMPLS Based Architecture for Mobility and End-to-End QoS Support in Fourth Generation Mobile NetworksAlejandro Quintero, Eduardo Del FrutosProblem statement: Next-generation mobile networks are evolving towards network architectures relying entirely on IP. Approach: These networks had to be scalable in order to support future IP traffic, namely new multimedia services and real time applications, while providing an effective mobility management mechanism to cope with increasingly mobile users. In addition to global connectivity, next-generation mobile networks will have to … …Journal of Computer Science, Vol. 5, Issue 4 · 30 Apr 2009 · 7,683 accessesView PDFCite
Research ArticleOpen accessIn the abstractDSP-128:Stream Cipher Based On Discrete Log Problem And Polynomial ArithmeticKhaled M. Suwais, Azman SamsudinDSP-128 is a new multithreaded stream cipher based on the intractability of the Discrete Logarithm Problem (DLP) with key size of 128-bit. The design of DSP-128 is divided into three stages: Initialization Stage, Keystream Generation Stage, and Encryption Stage. The design goal of DSP-128 is to come up with a secure stream cipher with good performance for data encryption. The … …American Journal of Applied Sciences, Vol. 5, Issue 7 · 31 Jul 2008 · 7,396 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number SystemSomayeh Timarchi, Omid Kavehei, Keivan NaviModulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the … …American Journal of Applied Sciences, Vol. 5, Issue 4 · 30 Apr 2008 · 7,561 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Reversible BCD Adder For Nanotechnology Based SystemsMajid Haghparast, Keivan NaviThis paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as &#34Copying Circuit&#34 to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all … …American Journal of Applied Sciences, Vol. 5, Issue 3 · 31 Mar 2008 · 10,135 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Hardware Implementation of High Speed FFT CoreM. Kannan, S. K. SrivatsaApplications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift … …Journal of Computer Science, Vol. 3, Issue 6 · 30 Jun 2007 · 7,227 accessesView PDFCite
Research ArticleOpen accessIn the abstractForecasting River Flow in the USA: A Comparison between Auto-Regression and Neural Network Non-Parametric ModelsAbdel K.M. Baareh, Alaa F. Sheta, Khaled A. KhnaifesForecasting a time series became one of the most challenging tasks to variety of data sets. The existence of large number of parameters to be estimated and the effect of uncertainty and outliers in the measurements makes the time series modeling too complicated. Recently, Artificial Neural Network (ANN) became quite successful tool to handle time series modeling problem. This paper … …Journal of Computer Science, Vol. 2, Issue 10 · 31 Oct 2006 · 6,962 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of an IP Library for the Synthesis of Image Compression SystemsChokri Souani, Ihsen Gazzah, Kamel BesbesTo design a hardware system we may use generated Intellectual Property (IP) cores from a library with optimized parameters. The IP parameters are area minimization, memory use optimization and speed acceleration. The designed system depends on such IP parameters. In this paper, we propose the design of an IP library optimized with different constraints. The created IPs may be used … …Journal of Computer Science, Vol. 2, Issue 9 · 30 Sep 2006 · 6,458 accessesView PDFCite