Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System
Somayeh Timarchi, Omid Kavehei & Keivan Navi
American Journal of Applied Sciences, Volume 5, Issue 4, pp. 312–319 · doi.org/10.3844/ajassp.2008.312.319
Abstract
Modulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and delay.
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Timarchi, S., Kavehei, O. & Navi, K. (2008). Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System. American Journal of Applied Sciences, 5(4), 312–319. https://doi.org/10.3844/ajassp.2008.312.319
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