Design of an IP Library for the Synthesis of Image Compression Systems

To design a hardware system we may use generated Intellectual Property (IP) cores from a library with optimized parameters. The IP parameters are area minimization, memory use optimization and speed acceleration. The designed system depends on such IP parameters. In this paper, we propose the design of an IP library optimized with different constraints. The created IPs may be used to implement optimized hardware architecture for discrete wavelet transform. Here, we take as a realization example the one dimension Discrete Wavelet Transform (DWT) with multi-resolution-level decomposition. We show that it is possible to design a hardware system with adjusted constraints. Moreover, it is possible to merge different structures. The design results in very flexible system architectures.