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Research ArticleOpen accessEvery word in the titleDESIGN OF HIGH-SPEED PARALLEL IN PARALLEL OUT SHIFT REGISTER USING ALGAAS/GAAS MODFET TECHNOLOGYV. Ganesan, K. S. ShajiThis study enumerates the efficient design and analysis of Parallel In Parallel Out (PIPO) shift register using AlGaAs/GaAs MODFET D Flip-flop. The transient and power analysis are obtained with operating voltage at 1.3 V for the D flip-flop and PIPO shift register using pspice tool. There are many issues facing while integrating many number of transistors like delay, power dissipation, … …American Journal of Applied Sciences, Vol. 11, Issue 8 · 8 May 2014 · 7,146 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. Nirmal KumarProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testing the architectures which need … …Journal of Computer Science, Vol. 8, Issue 6 · 13 Mar 2012 · 7,765 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleBarriers to Research Utilization among Registered Nurses at Hamad Medical CorporationAbdulqadir J. Nashwan, Ahmad A. Abujaber, Dana B. MansourThis study aimed to determine the barriers to research utilization from HMC registered nurses' perspectives. This quantitative descriptive study used a newly developed 25-item questionnaire. The questions were categorized into three domains: Nurse-related, System-related and Research-related Barriers. The questionnaire was distributed electronically via e-mail service to all registered nurses in Hamad Medical Corporation (HMC) (N = 5000). About 901 responses … …International Journal of Research in Nursing, Vol. 7, Issue 2 · 1 Dec 2016 · 8,130 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleUltra Low Power Single Edge Triggered Delay Flip Flop Based Shift Registers Using 10-Nanometer Carbon Nano Tube Field Effect TransistorRavi Thiyagarajan, Kannan VeerappanCarbon Nano Tube Field Effect Transistor is currently considered as promising successor of Metal Oxide Semiconductor Field Effect Transistor. The scaling down of the Metal Oxide Semiconductor device faced serious limits like short channel effect, tunnelling through gate oxide layer, associated leakage currents and power dissipation when its dimension shrink down to 22 nanometer range. Further scaling of Metal Oxide … …American Journal of Applied Sciences, Vol. 10, Issue 12 · 14 Oct 2013 · 6,749 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleRegister-Specific Collocational Constructions in English and Spanish: A Usage-Based ApproachGloria Corpas PastorConstructions are usage-based, conventionalised pairings of form and function within a cline of complexity and schematisation. Most research within Construction Grammar has focused on the monolingual description of schematic constructions: Mainly in English, but to a lesser extent in other languages as well. By contrast, very little constructional analyses have been carried out across languages. In this study we will … …Journal of Social Sciences, Vol. 11, Issue 3 · 13 Jul 2015 · 9,705 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Transition Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. NirmalKumar, T. MayilsamyProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 21 Jul 2012 · 7,357 accessesView PDFCite
Research ArticleOpen accessIn the keywordsEfficient Reversible Montgomery Multiplier and Its Application to Hardware CryptographyNoor Muhammed Nayeem, Lafifa Jamal, Hafiz Md. Hasan BabuProblem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not … …Journal of Computer Science, Vol. 5, Issue 1 · 31 Jan 2009 · 7,852 accessesView PDFCite
Research ArticleOpen accessIn the keywordsUsing Combinational Circuits for Control PurposesMaher A. Nabulsi, Mohammed A.F. Al-HusainyProblem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of … …Journal of Computer Science, Vol. 5, Issue 7 · 31 Jul 2009 · 7,237 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Power Hardware Implementation of High Speed FFT CoreM. Kannan, S. K. SrivatsaApplications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallel-pipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift … …Journal of Computer Science, Vol. 3, Issue 6 · 30 Jun 2007 · 7,227 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Secure Framework for Decentralized Digital Lockers Using Blockchain TechnologyYassir Farooqui, Syed Ibad Ali, Kishori Shekokar et al.In the age of digital transformation, the Decentralized Digital lockers provide as an innovative combination of blockchain This paper presents a decentralized digital locker system that combines blockchain technology with a user-friendly web application to securely store and manage digital assets. By using the Ethereum blockchain, the platform ensures strong security and unchangeable records. Users can easily register, store, and … …Journal of Computer Science, Vol. 21, Issue 9 · 23 Oct 2025 · 2,929 accessesView PDFCite