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24 results for “delay digit”
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Research ArticleOpen accessIn the abstractA Novel Exploitation of Errors in Redundant Residue Number System ArchitectureYaw AfriyieResidue Number System (RNS) is an unweighted number system that symbolizes big integers with smaller numbers. It can perform operations in particular addition and multiplication in parallel. Because of this property, RNS is extensively used in communication, Finite Impulse Response (FIR), cryptography and signal processing devices. The transfer of data in digital channels is very important for some critical applications … …American Journal of Applied Sciences, Vol. 18, Issue 1 · 30 Jun 2021 · 7,616 accessesView PDFCite
Research ArticleOpen accessIn the abstractA 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCSBakoune Pierre Hypolite, Wembe Tafo Evariste, Moukengue Imano AdolpheThis paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results … …American Journal of Engineering and Applied Sciences, Vol. 12, Issue 2 · 6 May 2019 · 7,671 accessesView PDFCite
Research ArticleOpen accessIn the abstractSynthesis of Optimal Incoherent Subcarrier Tracking of BOC(1,1) Navigation SignalsAlexandr Ivanovich PerovNavigation receivers of global positioning systems that are operated in complex electromagnetic environment must have an increased noise immunity characteristic. One way of such noise immunity rising is to use incoherent operating mode of navigation receiver. There are known processing algorithms for navigation signals with Binary Phase Shift Keying (BPSK) modulation. But in the near-term outlook Global Navigation Satellite Systems … …American Journal of Applied Sciences, Vol. 13, Issue 9 · 26 Sep 2016 · 7,166 accessesView PDFCite
Research ArticleOpen accessIn the abstractIMPROVING THE PERFORMANCE AND REDUCING BIT ERROR RATE ON WIRELESS DEEP FADING ENVIRONMENT RECEIVERSK. Jayanthi, V. P. Arunachalam, C. VasanthanayakiOne of the major challenges in wireless communication system is increasing complexity and reducing performance in detecting the received digital information in indoor and outdoor Environments. Consequently to overcome this problem we analyze the delay performance of a multiuser with perfect channel state information transmitting data on deep fading environment. In this proposed system, the Wireless Deep Fading Environment (WDFE) … …Journal of Computer Science, Vol. 10, Issue 3 · 29 Nov 2013 · 7,100 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,078 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of an Error Tolerant AdderA. N. Jayanthi, C. S. RavichandranProblem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 13 Mar 2012 · 7,249 accessesView PDFCite
Research ArticleOpen accessIn the abstractStabilization of a Nonlinear Delay SystemWalid Arouri, Elyes Maherzi, Mongi Besbes, Houda Ben Attia SethomProblem statement: The analysis and control of delayed systems are becoming more and more research topics in progress. This is mainly due to the fact that the delay is frequently encountered in technological systems. This can affect their significantly operations. Most control command laws are based on current digital computers and delays are intrinsic to the process or in the … …American Journal of Applied Sciences, Vol. 9, Issue 3 · 31 Jan 2012 · 6,844 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the abstractTransient Response of a Novel Displacement Transducer for Magnetic Levitation SystemMrunal Deshpande, Badrilal MathurProblem statement: In magnetic levitation system, position sensors are used to obtain a voltage proportional to the position of the suspended object. This is an essential feedback signal for stabilizing the system. These sensors make the system clumsy and prone to failures. To eliminate any physical attachment on the levitated object for the purpose of measuring its displacement, a novel … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 5 Oct 2011 · 7,235 accessesView PDFCite