4 results for “adder cells”

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Research ArticleOpen accessIn the keywordsDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,155 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsDesign and Analysis of Adders using Nanotechnology Based Quantum dot Cellular AutomataS. Karthigai Lakshmi, G. AthishaProblem statement: The area and complexity are the major issues in circuit design. Here, we propose different types of adder designs based on Quantum dot Cellular Automata (QCA) that reduces number of QCA cells and area compare to previous designs. The quantum dot cellular automata is a novel computing paradigm in nanotechnology that can implement digital circuits with faster speed, … …Journal of Computer Science, Vol. 7, Issue 7 · 30 Jun 2011 · 7,311 accessesView PDF Cite

Research ArticleOpen accessIn the abstractA Novel Fault-Tolerant Majority Gate Architecture for Robust Operation in QCA-Based Nano CircuitsAmi Patel, Vrushank Shah, Dipti KhurgeQuantum Dot Cellular Automata (QCA) is one of the promising alternatives to the traditional CMOS technologies for next-generation nanocomputing, which can be integrated at a higher density and has a higher possibility of low power consumption. Fabrication defects, environmental noise, and fault tolerance, especially in larger circuits, are challenging for practical implementation of QCA circuits. A new Fault-Tolerant Majority Gate … …Journal of Computer Science, Vol. 22, Issue 7 · 7 Jul 2026 · 1,194 accessesView PDF Cite

Research ArticleOpen accessIn the abstractLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDF Cite