Research ArticleOpen accessPhrase in the titleParallel Memetic Algorithm for VLSI Circuit Partitioning Problem using Graphical Processing UnitsP. Subbaraj, P. SivakumarProblem statement: Memetic Algorithm (MA) is a form of population-based hybrid Genetic Algorithm (GA) coupled with an individual learning procedure capable of performing local refinements. Here we used genetic algorithm to explore the search space and simulated annealing as a local search method to exploit the information in the search region for the optimization of VLSI netlist bi-Partitioning problem. However, … …Journal of Computer Science, Vol. 8, Issue 5 · 27 Feb 2012 · 7,090 accessesView PDFCite
Research ArticleOpen accessIn the keywordsAN EFFICIENT CELL PLACEMENT USING GRAVITATIONAL SEARCH ALGORITHMSRose Al Qasem, Taisir EldosIn modern chip design, cell placement is a stage in which cells representing well-defined functions are assigned physical locations, in a way that optimizes the total area and routing length. Cell placement is an NP-complete problem and the exact solution is generally far from reach for a practically sized instance. Hence, diversified heuristic algorithms are used to solve this problem. … …Journal of Computer Science, Vol. 9, Issue 8 · 25 Jun 2013 · 7,371 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Power Analog Multiplier Using MifgmosK. Duraisamy, U. RagavendranA novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is … …Journal of Computer Science, Vol. 9, Issue 4 · 14 May 2013 · 6,343 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number SystemSomayeh Timarchi, Omid Kavehei, Keivan NaviModulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the … …American Journal of Applied Sciences, Vol. 5, Issue 4 · 30 Apr 2008 · 7,561 accessesView PDFCite
Research ArticleOpen accessIn the abstractUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,612 accessesView PDFCite
Research ArticleOpen accessIn the abstractA PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTINGG. Nallathambi, S. RajaramThis study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect … …Journal of Mathematics and Statistics, Vol. 10, Issue 1 · 1 Feb 2014 · 6,741 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessIn the abstractAn Optimized Device Sizing of Analog Circuits using Particle Swarm OptimizationP. Prem Kumar, K. DuraiswamyProblem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most … …Journal of Computer Science, Vol. 8, Issue 6 · 19 Mar 2012 · 7,769 accessesView PDFCite
Research ArticleOpen accessIn the abstractFramework for Managing the Very Large Scale Integration Design ProcessSabah Al-Fedaghi, Eman Al-DwaisanProblem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as … …American Journal of Applied Sciences, Vol. 9, Issue 2 · 13 Dec 2011 · 7,491 accessesView PDFCite