2 results for “Testable realization”

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Research ArticleOpen accessIn the keywordsOR-Bridging Fault Identification and Diagnosis for Exclusive-OR Sum of Products Reed-Muller Canonical CircuitsV. Geetha, N. Devarajan, P. N. NeelakantanProblem statement: The faults in digital circuit can be classified broadly as single stuck-atfaults, multiple stuck-ay-faults, stuck-open faults, stuck-on faults, path delay faults, transient faults. Extensive research had been carried out in the field of testing of digital circuits to limit the number of input vectors. The cardinality of the test vectors proposed by many authors was quite high for … …Journal of Computer Science, Vol. 7, Issue 5 · 7 May 2011 · 7,151 accessesView PDF Cite

Research ArticleOpen accessAll words, across the recordSingle Stuck-At Fault Diagnosing Circuit of Reed-Muller Canonical Exclusive-Or Sum of Product Boolean ExpressionsP. N. Neelakantan, A. E. JeyakumarA testable design with a universal test set for single stuck-at zero and stuck-at one faults of Reed-Muller canonical form of Exclusive-OR sum of product logic expressions is proposed. The test circuit detects almost all the single stuck-at faults and needs only simple modifications for variations in the circuit under test. The number of test vectors is also quite small … …Journal of Computer Science, Vol. 2, Issue 7 · 31 Jul 2006 · 6,587 accessesView PDF Cite