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19 articles for “Low Power Circuits”
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Research ArticleOpen accessIn the keywordsDESIGN OF OPTIMAL CARRY SKIP ADDER AND CARRY SKIP BCD ADDER USING REVERSIBLE LOGIC GATESPraveena Murugesan, Thanushkodi KeppanagounderReversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate … …Journal of Computer Science, Vol. 10, Issue 5 · 26 Dec 2013 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Fault-Tolerant Majority Gate Architecture for Robust Operation in QCA-Based Nano CircuitsAmi Patel, Vrushank Shah, Dipti KhurgeQuantum Dot Cellular Automata (QCA) is one of the promising alternatives to the traditional CMOS technologies for next-generation nanocomputing, which can be integrated at a higher density and has a higher possibility of low power consumption. Fabrication defects, environmental noise, and fault tolerance, especially in larger circuits, are challenging for practical implementation of QCA circuits. A new Fault-Tolerant Majority Gate … …Journal of Computer Science, Vol. 22, Issue 7 · 7 Jul 2026 · 1,194 accessesView PDFCite
Research ArticleOpen accessIn the abstractImproved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic SystemsAouatif Ibnelouad, Abdeljalil Elkari, Hassan Ayad, Mostafa MjahedTo be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic … …Journal of Computer Science, Vol. 16, Issue 5 · 5 Jun 2020 · 7,520 accessesView PDFCite
Review ArticleOpen accessIn the abstractNikola TESLARelly Victoria Virgil Petrescu, Raffaella Aversa, Antonio Apicella et al.Nicolae Tesla, has remained and spent most of his life, making it hard to pronounce "Teslea"), is considered to be the inventor of the alternating current and uncovered cableless power transmission. It is attributed to the transmission of energy through monophase, biphasic, polyphase alternating currents and transmission of non-wired energy by electromagnetic waves (oscillations) in the industrial alternating current frequency … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 4 · 6 Nov 2017 · 13,193 accessesView PDFCite
EditorialOpen accessIn the abstractWearable Technology: A New Era of Gadgetry InnovationHaider KhaleelToday, wearable technology comes in a wide variety of forms, from wrist and arm bands to eyewear, footwear and smart textiles. The number of wearable electronic devices available in today’s electronics market including smart watches, activity trackers, helmets and smart clothing seems to grow substantially. In fact, this technology is recognized as one of the hottest trends and one of … …American Journal of Engineering and Applied Sciences, Vol. 7, Issue 4 · 18 Apr 2015 · 7,477 accessesView PDFCite
Research ArticleOpen accessIn the abstractBit Error Rate Analysis of RS (7, 3) Coded Frequency Shift Keying Using SimulinkT.A. Shanmugasundaram, V. VijayabaskarBit Error Rate is an essential parameter to quantize the effectiveness of transceiver circuits used in low power, low duty cycle sensor nodes. BER can figure out their performance in terms of number of retransmissions, which keeps the node to consume its battery power undesirably rather than conserving it. Forward Error Correction schemes ensure the transceiver circuit to effectively perform … …American Journal of Applied Sciences, Vol. 12, Issue 2 · 25 Mar 2015 · 7,047 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. NirmalKumar, T. MayilsamyProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 21 Jul 2012 · 7,357 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,078 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. Nirmal KumarProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testing the architectures which need … …Journal of Computer Science, Vol. 8, Issue 6 · 13 Mar 2012 · 7,765 accessesView PDFCite