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15 results for “Hardware Description Language”
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Research ArticleOpen accessIn the keywordsHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite
Research ArticleOpen accessIn the keywordsFPGA Based SPWM Bridge InverterM. N. Md Isa, M.I. Ahmad, Sohiful A.Z. Murad, M.K. Md ArshadThis study presents methodology to generate sinusoidal pulse width modulation (SPWM) signal using Field Programmable Gate Array, FPGA technology. We discussed the unipolar switching scheme and the methodology to generate the signal with the predetermined switching frequencies. Simulation on the designed pulses was conducted using Altera Max Plus II simulation tools. This simulation method was used to get the desired … …American Journal of Applied Sciences, Vol. 4, Issue 8 · 31 Aug 2007 · 7,396 accessesView PDFCite
Research ArticleOpen accessIn the abstractConceptual Modeling for Computer Organization and ArchitectureSabah Al-FedaghiUnderstanding computer system hardware, including how computers operate, is essential for undergraduate students in computer engineering and science. Literature shows students learning computer organization and assembly language often find fundamental concepts difficult to comprehend within the topic materials. Tools have been introduced to improve students’ comprehension of the interaction between computer architecture, assembly language and the operating system. One such … …Journal of Computer Science, Vol. 17, Issue 2 · 22 Feb 2021 · 8,913 accessesView PDFCite
Research ArticleOpen accessIn the abstractImproved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic SystemsAouatif Ibnelouad, Abdeljalil Elkari, Hassan Ayad, Mostafa MjahedTo be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic … …Journal of Computer Science, Vol. 16, Issue 5 · 5 Jun 2020 · 7,520 accessesView PDFCite
Research ArticleOpen accessIn the abstractVHDL DESIGN AND HARDWARE REALIZATION OF HYBRIDARTIFICIAL INTELLIGENCE ARCHITECTURERajeswaran Nagalingam, Tenneti Madhu, Munagala SuryakalavathiEvolutionary Algorithms (EA) use Genetic Algorithm (GA) in many optimization problems to efficiently compute the function value in less time. In this study the weight optimization of the Artificial Neural Net-work (ANN), using the Back Propagation Network (BPN), is tested and presented with GA. The combined architecture of Neuro-Genetic (Hybrid Artificial Intelligence) approach is proposed and simulated results are provided … …American Journal of Applied Sciences, Vol. 11, Issue 5 · 24 Feb 2014 · 6,566 accessesView PDFCite
Research ArticleOpen accessIn the abstractMulticore Based Open Loop Motor Controller Embedded System for Permanent Magnet Direct Current MotorK. Baskaran, K.S. Vijula GraceProblem statement: In an advanced electronics world most of the applications are developed by microcontroller based embedded system. Approach: Multicore processor based motor controller was presented to improve the processing speed of the controller and improve the efficiency of the motor by maintaining constant speed. It was based on the combination of Cortex processor (Software core) and Field Programmable Gate … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 22 Mar 2012 · 7,035 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering ApplicationsMd. Syedul Amin, Md. Mamun, Labonnah F. RahmanProblem statement: Finite Impulse Response (FIR) filters are widely used in various DSP applications. The design of digital FIR filters is a very basic problem in digital signal processing. A FIR filter with multiple operation capability is certainly very useful for any real-time filtering applications. This article presents a multipurpose FIR filter design modeled by the hardware description language VHDL … …American Journal of Applied Sciences, Vol. 8, Issue 12 · 11 Oct 2011 · 7,150 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Single Core Hardware Module of a Data Compression Scheme Using Prediction by Partial Matching TechniqueJubayer Jalil, Md. Mamun, Mohd. Marufuzzaman, Hafizah HusainProblem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,255 accessesView PDFCite
Research ArticleOpen accessIn the abstractEfficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAsMohammed H. Al MijalliProblem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (28) based SBoxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). … …American Journal of Applied Sciences, Vol. 8, Issue 8 · 18 Jul 2011 · 6,975 accessesView PDFCite