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84 articles for “RF Circuits”
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Research ArticleOpen accessIn the abstractGate Replacement Technique for Reducing Leakage Current in Wallace Tree MultiplierNaveen Raman, ThanushkodiLeakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace … …Journal of Computer Science, Vol. 9, Issue 2 · 30 Mar 2013 · 6,763 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessIn the abstractAn Overview of Direction-of-Arrival Estimation using an Antenna Array with Four ElementsLotfi Osman, Imen Sfar, Ali GharsallahThe Direction-of-Arrival (DOA) estimation techniques using antenna arrays are applied in large areas of research fields and have received great attention in literature. Mobile communication, Sonar and Radar are just some examples among a large number of possible applications. For example, in military application, it is very important to recognize the direction of any threat. Another example of commercial application … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 14 Dec 2012 · 7,777 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Pass Band Filter in Hybrid Architecture Planar/Non-Radiative Dielectric Waveguide Integration TechnologyGharssallah Ali, Harizi HanenProblem statement: The expansion of RF, microwave and millimeter devices has revolutionized today’s ommunication and sensor systems. Low-cost, high-performance and mass producible millimeter wave technologies are vital for commercial broadband systems. Challenging issues are commonly faced in the design of low-loss integrated circuits for example high-Q band pass filter, which the planar technique is fundamentally limited in performance. Approach: In … …American Journal of Applied Sciences, Vol. 9, Issue 10 · 10 Aug 2012 · 7,092 accessesView PDFCite
Research ArticleOpen accessIn the abstractEffect of Doping Position on the Active Silicon-on-Insulator Micro-Ring Resonator Based on Free Carrier InjectionB. Mardiana, Sahbuddin Shaari, P. Susthitha Menon et al.Problem statement: Metal interconnects have become significant limitation on the scaling of CMOS technologies in electronics integrated circuit. Silicon photonics has offers great potential to overcome this critical bottleneck due to the advantages of optical interconnects. Silicon-based optical micro-ring resonator is promising basic element of future electronic-photonic integrated circuits because of its wide applications on photonic devices such as modulator, … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 9 Aug 2012 · 7,342 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. NirmalKumar, T. MayilsamyProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 21 Jul 2012 · 7,357 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Field Programmable Gate Array Based Emulators for Motor Control ApplicationsAhmed Ben Achballah, Slim Ben Othman, Slim Ben SaoudProblem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 12 Jun 2012 · 8,723 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. Nirmal KumarProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testing the architectures which need … …Journal of Computer Science, Vol. 8, Issue 6 · 13 Mar 2012 · 7,765 accessesView PDFCite
Research ArticleOpen accessIn the abstractSome Applications of Spanning Trees in Complete and Complete Bipartite GraphsS. N. DaoudProblem statement: The number of spanning trees τ(G) in graphs (networks) is an important invariant, it is also an important measure of reliability of a network. Approach: Using linear algebra and matrix analysis techniques to evaluate the associated determinants. Results: In this study we derive simple formulas for the number of spanning trees of complete graph Kn and complete bipartite … …American Journal of Applied Sciences, Vol. 9, Issue 4 · 15 Feb 2012 · 7,263 accessesView PDFCite
Research ArticleOpen accessIn the abstractFramework for Managing the Very Large Scale Integration Design ProcessSabah Al-Fedaghi, Eman Al-DwaisanProblem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as … …American Journal of Applied Sciences, Vol. 9, Issue 2 · 13 Dec 2011 · 7,491 accessesView PDFCite