62 results for “FPGA”

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Research ArticleOpen accessIn the abstractDesign and Implementation of Novel Artificial Neural Network Based Stock Market Forecasting System on Field-Programmable Gate ArraysMd. Syedul Amin, Md. Mamun, Fazida Hanim Hashim et al.Problem statement: Multiagent system is very proficient and has rules well-suited for financial forecast with its neural network. In financial forecasting, the approach for rules extractions is less pertinent and involves algorithms which are complex. The unsupervised network method lacks in comprehensibility and leads to ambiguity. Approach: The application of neural network technology to real-time processing of financial market analysis … …American Journal of Applied Sciences, Vol. 8, Issue 10 · 12 Sep 2011 · 7,627 accessesView PDF Cite

Research ArticleOpen accessIn the abstractHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,443 accessesView PDF Cite

Research ArticleOpen accessIn the abstractLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDF Cite

Research ArticleOpen accessIn the abstractArchitecture of Low Power Energy Harvester Using Hybrid Input of Solar and Thermal for Laptop or Notebook: A ReviewHanani Mohamed Nadzirin, Jahariah Sampe, Muhammad Shabiul Islam, Noorfazila KamalThis paper aims to develop and design the architecture of Low Power Hybrid Energy Harvester (LPHEH) using the hybrid input of solar and thermal that can be harvested for self-powered laptop or notebook. This research will focus on the development of the high performance boost power converter to power up any laptop or notebook and design power management system of … …American Journal of Applied Sciences, Vol. 13, Issue 9 · 11 Sep 2016 · 7,636 accessesView PDF Cite

Review ArticleOpen accessIn the abstractArchitecture of an Ultra-Low-Power Fully Autonomous Universal Power Conditioner of Energy Harvester for Wireless Sensor Networks: A ReviewYeo Kim Heng, Md. Shabiul Islam, Susthitha Menon et al.A fully autonomous Universal Power Conditioner (UPC) that can accept energy from any micro-energy harvester (e.g., photovoltaic, thermoelectric, electromagnetic, piezoelectric etc.) is proposed. Generally, UPC removes the need of multiple optimized source specific converters. But, the proposed UPC architecture will be Ultra-Low-Power (ULP) with maximized efficiency to support the low energy levels generated by harvesting sources. This UPC uses a … …American Journal of Applied Sciences, Vol. 13, Issue 3 · 28 Mar 2016 · 7,782 accessesView PDF Cite

Research ArticleOpen accessIn the abstractA RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESST. Yasodha, I. Jacob Raglend, K. Meena Alias JeyanthiA novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme … …American Journal of Applied Sciences, Vol. 11, Issue 6 · 29 Mar 2014 · 6,699 accessesView PDF Cite

Research ArticleOpen accessIn the abstractApplication Specific Integrated Circuits Design and Implementation of Rademacher and Walsh FunctionsA. Abbasi, A. R.M. Alamoud, S. A. AbbasiThe orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today’s DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell … …American Journal of Engineering and Applied Sciences, Vol. 6, Issue 4 · 7 Jan 2014 · 7,340 accessesView PDF Cite

Research ArticleOpen accessIn the abstractOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,010 accessesView PDF Cite

Research ArticleOpen accessIn the abstractVHDL Modeling, Simulation and Prototyping of a Novel Arbitrary Signal Generation SystemS. A. Abbasi, A. R.M. Alamoud, J.M. Al ShahraniProblem statement: Arbitrary signal generators play an important role in many applications. Several different techniques utilizing both analog and digital approaches are being used for the generation of periodic signals. However, all of them suffer from many drawbacks. In this study, we present modeling, simulation and prototyping of a novel periodic arbitrary signal generation system using FPGAs. The proposed system … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,755 accessesView PDF Cite

Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDF Cite