A RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESS
T. Yasodha1, I. Jacob Raglend2 & K. Meena Alias Jeyanthi3 Show affiliations
- Department of Electronics and Communication Engineering, Christian College of Engineeringand Technology, India
- Department of Electrical and Electronics Engineering, Noorul Islam University, Nagercoil, Tamilnadu, India
- Department of Electronics and Communication Engineering, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India
American Journal of Applied Sciences, Volume 11, Issue 6, pp. 883–887 · doi.org/10.3844/ajassp.2014.883.887
Abstract
A novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme in MIMO-High Speed Downlink Packet Access (MIMO-HSDPA). To attain effective performance close to shannon limit in a multi channel system, flexible reconfigurable architecture is realized with 28 nm cyclone V GX 5CGXFC5C6 FPGA. We achieved throughput of 13.5 Mbps compared with the conventional HSDPA standards while consuming 53 mW.
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Yasodha, T., Raglend, I. J. & Jeyanthi, K. M. A. (2014). A RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESS. American Journal of Applied Sciences, 11(6), 883–887. https://doi.org/10.3844/ajassp.2014.883.887
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