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564 articles for “Architect”
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Research ArticleOpen accessIn the abstractLow Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number SystemSomayeh Timarchi, Omid Kavehei, Keivan NaviModulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the … …American Journal of Applied Sciences, Vol. 5, Issue 4 · 30 Apr 2008 · 7,563 accessesView PDFCite
Research ArticleOpen accessIn the abstractIrregular Class of Multistage Interconnection Network in Parallel ProcessingSandeep Sharma, K. S. Kahlon, P. K. Bansal, Kawaljeet SinghA major problem in designing a large-scale parallel and distributed system was the construction of an Interconnection Network (IN) to provide inter-processor communication. One of the biggest issues in the development of such a system was the development of an effective architecture and algorithms that have high reliability, give good performance (even in the presence of faults), low cost, low … …Journal of Computer Science, Vol. 4, Issue 3 · 31 Mar 2008 · 7,062 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Reversible BCD Adder For Nanotechnology Based SystemsMajid Haghparast, Keivan NaviThis paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as &#34Copying Circuit&#34 to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all … …American Journal of Applied Sciences, Vol. 5, Issue 3 · 31 Mar 2008 · 10,138 accessesView PDFCite
Research ArticleOpen accessIn the abstractImproving Response Time of Authorization Process of Credit Card System Using Multi-Threading and Shared-Memory Pool TechniquesSiti H.A. Hamid, Mohd H.N.M. Nasir, Wong Y. Ming, Hazrina HassanCurrent credit card authorization was developed on single-threaded model whereby authentication process takes longer time to respond due to sequential process of card's risk management profile and its limitation of handling huge number of simultaneous transactions at single point of time. As a result, the performance of the authorization system was affected during peak hours. This study presented an architectural … …Journal of Computer Science, Vol. 4, Issue 2 · 28 Feb 2008 · 7,238 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a ApplicationHarikrishnan Ramiah, Tun Zainal Azni ZulkifliThe paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor … …American Journal of Applied Sciences, Vol. 5, Issue 2 · 28 Feb 2008 · 7,297 accessesView PDFCite
Research ArticleOpen accessIn the abstractNimble Protein Sequence Alignment in Grid (NPSAG)K. Somasundaram, S. RadhakrishnanIn Bio-Informatics application, the analysis of protein sequence is a kind of computation driven science which has rapidly and quickly growing biological data. Also databases used in these applications are heterogeneous in nature and alignment of protein sequence using physical techniques is expensive, slow and results are not always guaranteed/accurate. So this application requires cross-platform, cost-effective and more computing power … …Journal of Computer Science, Vol. 4, Issue 1 · 31 Jan 2008 · 6,924 accessesView PDFCite
Research ArticleOpen accessIn the abstractFunctional Link Artificial Neural Network for Classification Task in Data MiningB. B. Misra, S. DehuriIn solving classification task of data mining, the traditional algorithm such as multi-layer perceptron takes longer time to optimize the weight vectors. At the same time, the complexity of the network increases as the number of layers increases. In this study, we have used Functional Link Artificial Neural Networks (FLANN) for the task of classification. In contrast to multiple layer … …Journal of Computer Science, Vol. 3, Issue 12 · 31 Dec 2007 · 60,801 accessesView PDFCite
Research ArticleOpen accessIn the abstractStructure and Performance of the Meta Inference EngineJean-Marc NIGRO, Yann BARLOYThis study presents the structure and the performance of a new inference engine: the MIE (Meta Inference Engine). It is able to manipulate not only the rules but also the metarules. The article first describes the architecture of the MIE and gives an example to illustrate its use. A comparison of performance between an RETE network and the MIE is … …Journal of Computer Science, Vol. 3, Issue 11 · 30 Nov 2007 · 6,894 accessesView PDFCite
Research ArticleOpen accessIn the abstractExploring Spatial ARM (Spatial Association Rule Mining) for Geo-Decision Support SystemRanjana Vyas, Lokesh Kumar Sharma, U. S. TiwaryGeographical Decision Support System (Geo-DSS) is a demanding field, since enormous amount of spatial data have been collected in various applications, ranging form Remote Sensing to GIS, Computer Cartography, Environmental Assessment and Planning. Although some efforts were made to combine spatial mining with Spatial Decision Support System but mostly researchers for spatial database are using a popular data mining approach-Apriori … …Journal of Computer Science, Vol. 3, Issue 11 · 30 Nov 2007 · 6,962 accessesView PDFCite
Research ArticleOpen accessIn the abstractAdaptive Resonance Theory 1 (ART1) Neural Network Based Horizontal and Vertical Classification of 0-9 Digits RecognitionMbaitiga ZacharieThis study describes the Adaptive Resonance Theory 1 (ART1), an efficient algorithm that emulates the self-organizing pattern recognition and hypothesis testing properties of the ART neural network architecture for horizontal and vertical classification of 0-9 digits recognition. In our approach the ART1 model can self-organize in real time producing stable and clear recognition while getting input patterns beyond those originally … …Journal of Computer Science, Vol. 3, Issue 11 · 30 Nov 2007 · 7,353 accessesView PDFCite