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45 results for “CMOS”
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Research ArticleOpen accessIn the abstractLow Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number SystemSomayeh Timarchi, Omid Kavehei, Keivan NaviModulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the … …American Journal of Applied Sciences, Vol. 5, Issue 4 · 30 Apr 2008 · 7,561 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a ApplicationHarikrishnan Ramiah, Tun Zainal Azni ZulkifliThe paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor … …American Journal of Applied Sciences, Vol. 5, Issue 2 · 28 Feb 2008 · 7,295 accessesView PDFCite
Research ArticleOpen accessIn the abstractA New Efficient-Silicon Area MDAC SynapseZied Gafsi, Nejib Hassen, Mongia Mhiri, Kamel BesbesUsing the binary representation ΣiDi2i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named … …American Journal of Applied Sciences, Vol. 4, Issue 6 · 30 Jun 2007 · 7,158 accessesView PDFCite
Research ArticleOpen accessIn the abstractAsynchronous NoC Router DesignSami Badrouchi, Abdelkrim Zitouni, Kholdoun Torki, Rached TourkiThe Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents an asynchronous NoC router, for use in 2-D mesh-connected networks. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the … …Journal of Computer Science, Vol. 1, Issue 3 · 30 Sep 2005 · 7,414 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Fully Integrated Dual-Band Low Noise Amplifier for IEEE 802.11 and Hiper LAN ApplicationMow Shouxian, Ma Jianguo, Yeo Kiat Seng, Do Manh AnhA fully-integrated dual-band Low Noise Amplifier (LNA), which can be used for IEEE 802.11 and Hiper LAN applications, was investigated in this paper. The proposed LAN was implemented entirely pm a single chip based on a standard 0.18 μm 1P6M CMOS process. It draws 13 mA current from a 1.5-V voltage supply and achieves power gains of 17 and 10 … …American Journal of Applied Sciences, Vol. 1, Issue 1 · 31 Mar 2004 · 7,288 accessesView PDFCite