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238 results for “Low-Power”
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Research ArticleOpen accessEvery word in the titleA PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTINGG. Nallathambi, S. RajaramThis study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect … …Journal of Mathematics and Statistics, Vol. 10, Issue 1 · 1 Feb 2014 · 6,747 accessesView PDFCite
Research ArticleOpen accessEvery word in the titlePeak to Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing System with a Significant Low ComplexityMahamod Ismail, J. S. Mandeep, Montadar Abas Taher, M. T. IslamThe Orthogonal Frequency Division Multiplexing (OFDM) has been widely used in many applications in the last decade. It provides good benefits compared to the single carrier systems. However, it has a bad property represented by the high-output Peak to Average Power Ratio (PAPR) which is considered as its major problem. There are many techniques to reduce the PAPR values such … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 20 Dec 2012 · 6,594 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHigh Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise ReductionT. S. Karthik, V. Jawahar Senthil KumarProblem statement: In any multimedia processor, controller may consume most of the on-chip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications … …Journal of Computer Science, Vol. 8, Issue 3 · 6 Jan 2012 · 7,179 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,618 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Analog Multiplier Using MifgmosK. Duraisamy, U. RagavendranA novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is … …Journal of Computer Science, Vol. 9, Issue 4 · 14 May 2013 · 6,347 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleLow Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number SystemSomayeh Timarchi, Omid Kavehei, Keivan NaviModulo 2n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the … …American Journal of Applied Sciences, Vol. 5, Issue 4 · 30 Apr 2008 · 7,563 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBit Error Rate Analysis of RS (7, 3) Coded Frequency Shift Keying Using SimulinkT.A. Shanmugasundaram, V. VijayabaskarBit Error Rate is an essential parameter to quantize the effectiveness of transceiver circuits used in low power, low duty cycle sensor nodes. BER can figure out their performance in terms of number of retransmissions, which keeps the node to consume its battery power undesirably rather than conserving it. Forward Error Correction schemes ensure the transceiver circuit to effectively perform … …American Journal of Applied Sciences, Vol. 12, Issue 2 · 25 Mar 2015 · 7,051 accessesView PDFCite
Research ArticleOpen accessIn the keywordsHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,487 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDESIGN OF OPTIMAL CARRY SKIP ADDER AND CARRY SKIP BCD ADDER USING REVERSIBLE LOGIC GATESPraveena Murugesan, Thanushkodi KeppanagounderReversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate … …Journal of Computer Science, Vol. 10, Issue 5 · 26 Dec 2013 · 6,683 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBER Performance and Data Throughput of Sinusoidal Template-Based Impulse-Radio Ultra Wideband Receivers for Wireless Body Area NetworksMohamad Abou El-Nasr, Heba ShabanWindowed sinusoidal template-based correlator receivers are good candidates for high-data rate low-power Ultra Wideband (UWB) systems. Their performance approaches the performance of optimal detectors and provides low-power consumption. However, the ultra short pulses of UWB technology makes it sensitive to timing-errors. In this paper, the Bit-Error-Rate (BER) performance and maximum allowable data throughput of Equally-Correlated Pulse Position Modulation (EC-PPM) modulation … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 30 May 2013 · 6,507 accessesView PDFCite