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53 articles for “Hardware Architecture”
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Research ArticleOpen accessIn the abstractVLSI Implementation of Channel Estimation for MIMO-OFDM TransceiverJoseph Gladwin Sekar, Salivahanan SankarappanIn this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 6,550 accessesView PDFCite
Research ArticleOpen accessIn the abstractFeasibility of Desktop Virtualization Per Software Services and Local Hardware Based on the Network ThroughputVitor Chaves De Oliveira, Inacio Henrique Yano, Alexandre De Assis Mota, Lia Toledo Moreira MotaIn recent years, virtualization computing has become a worldwide reality present in datacenters servers of most organizations. The motivations for the use of this solution are focused primarily on cost reduction and increases in availability, integrity and security of data. Based on these benefits, recently it was started the use of this technology for personal computers as well. That is, … …Journal of Computer Science, Vol. 9, Issue 7 · 15 Jun 2013 · 6,725 accessesView PDFCite
Research ArticleOpen accessIn the abstractEvaluation of Various Compiler Optimization Techniques Related to Mibench Benchmark ApplicationsJeyaraj Andrews, Thangappan SasikalaTuning compiler optimization for a given application of particular computer architecture is not an easy task, because modern computer architecture reaches higher levels of compiler optimization. These modern compilers usually provide a larger number of optimization techniques. By applying all these techniques to a given application degrade the program performance as well as more time consuming. The performance of the … …Journal of Computer Science, Vol. 9, Issue 6 · 6 Jun 2013 · 7,219 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. NirmalKumar, T. MayilsamyProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need … …American Journal of Applied Sciences, Vol. 9, Issue 9 · 21 Jul 2012 · 7,357 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Field Programmable Gate Array Based Emulators for Motor Control ApplicationsAhmed Ben Achballah, Slim Ben Othman, Slim Ben SaoudProblem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 12 Jun 2012 · 8,723 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-TestP. Sakthivel, A. Nirmal KumarProblem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testing the architectures which need … …Journal of Computer Science, Vol. 8, Issue 6 · 13 Mar 2012 · 7,765 accessesView PDFCite
Research ArticleOpen accessIn the abstractDynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive ImplementationHedi Abdelkrim, Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben SaoudProblem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using … …American Journal of Engineering and Applied Sciences, Vol. 5, Issue 1 · 18 Feb 2012 · 8,978 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign and Implementation of Novel Artificial Neural Network Based Stock Market Forecasting System on Field-Programmable Gate ArraysMd. Syedul Amin, Md. Mamun, Fazida Hanim Hashim et al.Problem statement: Multiagent system is very proficient and has rules well-suited for financial forecast with its neural network. In financial forecasting, the approach for rules extractions is less pertinent and involves algorithms which are complex. The unsupervised network method lacks in comprehensibility and leads to ambiguity. Approach: The application of neural network technology to real-time processing of financial market analysis … …American Journal of Applied Sciences, Vol. 8, Issue 10 · 12 Sep 2011 · 7,627 accessesView PDFCite
Research ArticleOpen accessIn the abstractOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,010 accessesView PDFCite