Research ArticleOpen accessIn the keywordsUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,612 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of 8-4 and 9-4 Compressors Forhigh Speed MultiplicationR. Marimuthu, Dhruv Bansal, S. Balamurugan, P. S. MallickThis study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order … …American Journal of Applied Sciences, Vol. 10, Issue 8 · 24 Jul 2013 · 7,213 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Fault-Tolerant Majority Gate Architecture for Robust Operation in QCA-Based Nano CircuitsAmi Patel, Vrushank Shah, Dipti KhurgeQuantum Dot Cellular Automata (QCA) is one of the promising alternatives to the traditional CMOS technologies for next-generation nanocomputing, which can be integrated at a higher density and has a higher possibility of low power consumption. Fabrication defects, environmental noise, and fault tolerance, especially in larger circuits, are challenging for practical implementation of QCA circuits. A new Fault-Tolerant Majority Gate … …Journal of Computer Science, Vol. 22, Issue 7 · 7 Jul 2026 · 1,194 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDFCite