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21 articles for “Xilinx”
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Research ArticleOpen accessIn the abstractPERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK CODE DECODER FOR LOW POWER APPLICATIONSM. Revathy, R. SaravananIn this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error-detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption … …American Journal of Applied Sciences, Vol. 11, Issue 4 · 30 Jan 2014 · 6,882 accessesView PDFCite
Research ArticleOpen accessIn the abstractERROR DETECTION SCHEMES FOR FINITE FIELD MULTIPLIERSB. Sargunam, R. DhanasekaranFinite field multipliers are widely used in the field of cryptography for the purpose of scalar multiplication. The outputs of the finite field multipliers may consist of errors due to certain natural radiations which further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for … …American Journal of Applied Sciences, Vol. 11, Issue 1 · 11 Dec 2013 · 6,913 accessesView PDFCite
Research ArticleOpen accessIn the abstractReconfigurable Hardware Architecture for Network Intrusion Detection SystemA. Kaleel Rahuman, G. AthishaIntrusion rule processing in reconfigurable hardware enables intrusion detection and prevention. The use of reconfigurable hardware for network security applications has great strides as Field Programmable Gate Array (FPGA) devices have provided larger and faster resources. This proposes architecture called “BV-TCAM” is presented, which is implemented for an FPGA-based Network Intrusion Detection Systems (NIDS). The BV-TCAM architecture combines the Ternary … …American Journal of Applied Sciences, Vol. 9, Issue 10 · 16 Aug 2012 · 6,981 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Transmitter for CDM Based 2×2 Multiple Input Multiple Output Channel Sounder for Multipath Delay MeasurementM. Habib Ullah, M. T. Islam, Mandeep Sing et al.Problem statement: Multiple Input Multiple Output (MIMO) wireless communication system is an innovative solution to improve the bandwidth efficiency by exploiting multipath-richness of the propagation environment. The degree of multipath-richness of the channel will determine the capacity gain attainable by MIMO deployment. Approach: Therefore, it is very important to have accurate knowledge of the propagation environment/radio channel before MIMO implement. … …American Journal of Applied Sciences, Vol. 9, Issue 1 · 24 Nov 2011 · 7,898 accessesView PDFCite
Research ArticleOpen accessIn the abstractVHDL Modeling, Simulation and Prototyping of a Novel Arbitrary Signal Generation SystemS. A. Abbasi, A. R.M. Alamoud, J.M. Al ShahraniProblem statement: Arbitrary signal generators play an important role in many applications. Several different techniques utilizing both analog and digital approaches are being used for the generation of periodic signals. However, all of them suffer from many drawbacks. In this study, we present modeling, simulation and prototyping of a novel periodic arbitrary signal generation system using FPGAs. The proposed system … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,755 accessesView PDFCite
Research ArticleOpen accessIn the abstractOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,924 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,443 accessesView PDFCite
Research ArticleOpen accessIn the abstractFPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision GatingA. Senthilkumar, A. M. NatarajanWith the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition … …Journal of Computer Science, Vol. 4, Issue 2 · 28 Feb 2008 · 7,315 accessesView PDFCite
Research ArticleOpen accessIn the abstractTeaching Computer Organization and Architecture Using Simulation and FPGA ApplicationsKasim M. Al-AubidyThis paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has … …Journal of Computer Science, Vol. 3, Issue 8 · 31 Aug 2007 · 7,100 accessesView PDFCite