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101 results for “RF Circuits”
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Research ArticleOpen accessEvery word in the titleOptimization of Test Scheduling and Test Access for ITC-02 SOC Benchmark CircuitsP. Sakthivel, R. Delhi Babu, P. NarayanasamyProblem statement: This study presented the optimized test scheduling and test access for ITC-02 SOC benchmark circuits using genetic algorithm. In the scheduling procedure of SOC, scheduling problem was formulated as a sequence of two problems and solved. Approach: Test access mechanism width was partitioned into two and three partitions and the applications of test vectors and test vector assignments … …Journal of Computer Science, Vol. 5, Issue 4 · 30 Apr 2009 · 7,315 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA New Approach of Almost Periodic Lumped Elements Circuits by an Iterative Method Using Auxiliary SourcesMohamed Karim Azizi, Lassaad Latrach, Nathalie Raveu et al.Nowadays, met materials with lumped or distributed elements are emerging and it is necessary to develop new techniques based on the following principles. The approach should be global and have to be formulated according to the existing classic formulations. In fact, the Wave Concept Iterative Process (WCIP) is systematically used in such application. On the other hand, the periodic medium … …American Journal of Applied Sciences, Vol. 10, Issue 11 · 5 Oct 2013 · 6,919 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDESIGN OF OPTIMAL CARRY SKIP ADDER AND CARRY SKIP BCD ADDER USING REVERSIBLE LOGIC GATESPraveena Murugesan, Thanushkodi KeppanagounderReversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate … …Journal of Computer Science, Vol. 10, Issue 5 · 26 Dec 2013 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel µ-Negative Metamaterial With Enhanced Rejection BandwidthHaider Raad, Hussain Al-Rizzo, Ayman Abbosh, Said AbushamlehIn this study, a novel planar µ-Negative (MNG) metamaterial structure based on Split Ring Resonators (SRRs) with improved rejection bandwidth is presented. A bridging technique is used to connect two SRR unit cells at the center to emulate a cascaded filter. The proposed structure achieved a -20 dB rejection bandwidth of 15.5% compared to 4.5% for the conventional SRRs which … …American Journal of Engineering and Applied Sciences, Vol. 6, Issue 2 · 3 Apr 2013 · 7,372 accessesView PDFCite
Research ArticleOpen accessIn the keywordsField Programmable Gate Arrays Based Realization of Truncated MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 6,694 accessesView PDFCite
Research ArticleOpen accessIn the keywordsSpartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay StudyMohammed H. Al MijalliProblem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be … …American Journal of Applied Sciences, Vol. 8, Issue 6 · 13 Jun 2011 · 6,428 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Power Analog Multiplier Using MifgmosK. Duraisamy, U. RagavendranA novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is … …Journal of Computer Science, Vol. 9, Issue 4 · 14 May 2013 · 6,343 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLow Cost Smart Sensor DesignTakialddin A. Al SmadiProblem statement: Sensor with local processing power that enables it to react to local conditions without having to refer back to the central controller. The size and the cost of smart sensor circuit have been reduced. Approach: The use of microcontroller, such as (PIC16C715), with an 8-bit ADC (Analogue to Digital Converter) in one chip. This reduction in the circuit … …American Journal of Engineering and Applied Sciences, Vol. 4, Issue 1 · 11 Feb 2016 · 7,574 accessesView PDFCite
Research ArticleOpen accessIn the keywordsField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBraun's Multipliers: Spartan-3AN based Design and ImplementationMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The … …Journal of Computer Science, Vol. 7, Issue 11 · 18 Aug 2011 · 6,909 accessesView PDFCite