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21 results for “Field Programmable Gate Array FPGA”
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Research ArticleOpen accessIn the keywordsA Real-time Image Processing with a Compact FPGA-based ArchitectureRidha Djemal, Didier Demigny, Rached TourkiThis study have presented a filed programmable gate array implementation of a real time video smoothing algorithm. In comparison with smoothing video techniques like deblocking filters in H.264 or smoothing in JPEG2000, the proposed method is implemented in hardware and its computational cost and complexity are reduced where all pixel processing related to uncompressed video is done on the fly. … …Journal of Computer Science, Vol. 1, Issue 2 · 30 Jun 2005 · 7,001 accessesView PDFCite
Research ArticleOpen accessIn the abstractSoftware Defined Radio Implementation of a QPSK Modulator/Demodulator in an Extensive Hardware Platform Based on FPGAs Xilinx ZYNQSérgio Bimbi Junior, Vitor Chaves de Oliveira, Gunnar Bedicks JuniorSoftware Defined Radio (SDR) technology enables wireless devices deployment with support to multiple interfaces in modulation formats and it has gained importance due to the current wireless standards proliferation. In order to activate these functionalities it is necessary to apply SDR inside a reconfigurable hardware such as the Field Programmable Gate Array (FPGA). In this study, design procedures developments are … …Journal of Computer Science, Vol. 11, Issue 4 · 2 Jun 2015 · 8,813 accessesView PDFCite
Research ArticleOpen accessIn the abstractSOPC BASED WIRELESS REMOTE PATIENT MONITORING USING ULTRA LIGHTWEIGHT CRYPTOGRAPHYA. Arun, P. Nirmal KumarRemote Patient Monitoring (RPM) provides flexible and powerful patient surveillance through wearable devices at anytime and anywhere. This can be achieved by using a Body Sensor Network (BSN), which is deployed on a human body for monitoring the healthcare. The mobile healthcare management with increased feasibility and handiness introduced several noteworthy challenges for the provider, policy makers, patient and hospitals. … …Journal of Computer Science, Vol. 10, Issue 10 · 8 May 2014 · 7,194 accessesView PDFCite
Research ArticleOpen accessIn the abstractDESIGN AND IMPLEMENTATION OF GLOBAL POSITIONING SYSTEM RECEIVER IN FIELD PROGRAMMABLE GATE ARRAY WITH SHORT MESSAGE SERVICEGovindaraju Kavya, Vittal Thulasi BaiIn recent years, survival rate from myocardial infarction and bundle branch block has been increased due to the advancements in medical field. Continuous monitoring and location management of these patients becomes an essential task. Hence this study aims in design and development of GPS in a Field Programmable Gate Array (FPGA) and interfaced with a GSM modem to transmit the … …Journal of Computer Science, Vol. 10, Issue 1 · 12 Nov 2013 · 7,563 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Architecture of Maximum Power Point Tracking for Ultra-Low-Power Based Hybrid Energy Harvester in Ubiquitous Devices: A ReviewMichelle Lim Sern Mi, Sawal Hamid Muhammad Ali, Md Shabiul IslamThis research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 7,155 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Arrays Based Realization of Truncated MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 6,694 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Array -Based System-on-Chip for Real-Time Power Process ControlAhmed Karim Ben Salem, Slim Ben Othman, Slim Ben SaoudProblem Statement: Nowadays Real-Time (RT) embedded control applications require not just higher performance but more flexibility as well without increasing cost and resources. Approach: In this study we presented a promising co-design and implementation of control solution. We developed flexible solution using software control algorithms coupled with an embedded RT kernel on powerful embedded processor cores, combined with reconfigurable logic … …American Journal of Applied Sciences, Vol. 7, Issue 1 · 31 Jan 2010 · 7,455 accessesView PDFCite
Research ArticleOpen accessIn the abstractField Programmable Gate Array-Based Pulse-Width Modulation for Single Phase Active Power FilterN. A. Rahim, Z. IslamProblem statement: The design and implementation of a sinusoidal Pulse-Width Modulation (PWM) generator for a single-phase hybrid power filter is presented. Approach: The PWM was developed in an Altera® Flex 10 K Field Programmable Gate Array (FPGA) and the modulation index was selected by calculating the DC bus voltage of the active filter through a digital controller, by Proportional-Integral-Derivative (PID) … …American Journal of Applied Sciences, Vol. 6, Issue 9 · 30 Sep 2009 · 7,293 accessesView PDFCite