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7 articles for “silicon chip”
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Research ArticleOpen accessIn the keywordsLow Cost Smart Sensor DesignTakialddin A. Al SmadiProblem statement: Sensor with local processing power that enables it to react to local conditions without having to refer back to the central controller. The size and the cost of smart sensor circuit have been reduced. Approach: The use of microcontroller, such as (PIC16C715), with an 8-bit ADC (Analogue to Digital Converter) in one chip. This reduction in the circuit … …American Journal of Engineering and Applied Sciences, Vol. 4, Issue 1 · 11 Feb 2016 · 7,574 accessesView PDFCite
Research ArticleOpen accessIn the abstractCoupling Routing Algorithm and Data Encoding for Low Power Networks on ChipMaurizio Palesi, Davide Patti, Giuseppe Ascia et al.The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main objectives. In this study we focus on two important non functional metrics, namely, power dissipation and energy consumption. We propose a selection policy … …Journal of Computer Science, Vol. 11, Issue 3 · 4 May 2015 · 6,928 accessesView PDFCite
Research ArticleOpen accessIn the abstractMolecular Dynamics Investigation of Cutting Force in Nanometric Cutting of Monocrystalline SiliconY.H. Chen, F.Z. Fang, X.D. Zhang, X.T. HuProblem statement: Ultra-precision machining of monocrystalline silicon has become tremendously important in microelectronic, micromechanical and optical element manufacturing and the mechanism of nanometric cutting monocrystalline silicon has been a focused research topic. Molecular Dynamics (MD) simulation is developed as an effective way for studying the material removal process at nanometric scale. Approach: Molecular Dynamics (MD) simulation of nanometric cutting is … …Current Research in Nanotechnology, Vol. 1, Issue 2 · 21 Jun 2011 · 8,403 accessesView PDFCite
Research ArticleOpen accessIn the abstractOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,010 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless ReceiversRozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman et al.Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,815 accessesView PDFCite
Research ArticleOpen accessIn the abstractOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,924 accessesView PDFCite
Research ArticleOpen accessIn the abstractAsynchronous NoC Router DesignSami Badrouchi, Abdelkrim Zitouni, Kholdoun Torki, Rached TourkiThe Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents an asynchronous NoC router, for use in 2-D mesh-connected networks. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the … …Journal of Computer Science, Vol. 1, Issue 3 · 30 Sep 2005 · 7,414 accessesView PDFCite