Research ArticleOpen accessIn the keywordsLow Power Multiplier Design Using Latches and Flip-FlopsC. N. Marimuthu, P. ThangarajProblem statement: Power dissipation is designated as critical parameter in modern VLSI design field. In VLSI implementation low power concept is necessary to meet Moore’s law and to produce consumer electronics with more back up and less weight. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power which is the … …Journal of Computer Science, Vol. 6, Issue 10 · 30 Jul 2010 · 7,372 accessesView PDFCite
Research ArticleOpen accessIn the abstractLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDFCite
Research ArticleOpen accessIn the abstractCoupling Routing Algorithm and Data Encoding for Low Power Networks on ChipMaurizio Palesi, Davide Patti, Giuseppe Ascia et al.The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main objectives. In this study we focus on two important non functional metrics, namely, power dissipation and energy consumption. We propose a selection policy … …Journal of Computer Science, Vol. 11, Issue 3 · 4 May 2015 · 6,928 accessesView PDFCite