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22 articles for “high speed architecture”
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Research ArticleOpen accessEvery word in the titleA RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESST. Yasodha, I. Jacob Raglend, K. Meena Alias JeyanthiA novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme … …American Journal of Applied Sciences, Vol. 11, Issue 6 · 29 Mar 2014 · 6,699 accessesView PDFCite
Research ArticleOpen accessIn the keywordsTowards an Integrated Intrusion Detection Monitoring in High Speed NetworksHassen SallayProblem statement: Security Management has become a critical aspect for large scale distributed systems. Particularly, recent Distributed Intrusion Detection Systems (DIDS) schemes in High Speed Networks (HSN) have raised new serious management problems and challenges. Increasing the effectiveness of IDS monitoring is primordial to satisfy the restrictive constraints in such large multi-domains environment for narrow context of HSN. Approach: We … …Journal of Computer Science, Vol. 7, Issue 7 · 30 Jun 2011 · 6,560 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing ArchitecturesN. Ramadass, S. Natarajan, J. Raja Paul PerinbamEmerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic … …Journal of Computer Science, Vol. 3, Issue 10 · 31 Oct 2007 · 6,727 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesigning the Future: A Blockchain-Based Framework for Transparent and Secure ElectionsJayesh Solanki, Divyakant MevaBlockchain-based electronic voting systems have been identified as a solution to enhance the transparency, security, and efficiency of modern electoral processes. However, the existing system has three major problems, which include scalability, privacy issues, and cybersecurity attacks. The researcher proposed an innovative solution to develop an electronic voting system with enhanced security, scalability, and transparency of voters' information. This paper … …Journal of Computer Science, Vol. 22, Issue 6 · 16 Jun 2026 · 1,291 accessesView PDFCite
Research ArticleOpen accessIn the abstractTowards a Generic Multimodal Architecture for Batch and Streaming Big Data IntegrationSiham Yousfi, Maryem Rhanoui, Dalila ChiadmiBig Data are rapidly produced from various heterogeneous data sources. They are of different types (text, image, video or audio) and have different levels of reliability and completeness. One of the most interesting architectures that deal with the large amount of emerging data at high velocity is called the lambda architecture. In fact, it combines two different processing layers namely … …Journal of Computer Science, Vol. 15, Issue 1 · 31 Jan 2019 · 7,646 accessesView PDFCite
Research ArticleOpen accessIn the abstractOptimised Implementation of Dense Stereo Correspondence for Resource Limited HardwareDeepambika Vadekkettathu Anirudhan, Malangai Abdul RahimanComputer stereo vision is a passive sensing technique that helps to recover 3D information of an environment from 2D images. The stereo correspondence is a challenging task that finds out matching pixels between the stereo image pair based on Lambertian criteria and its result is a disparity space image. The depth of the objects from the camera can be calculated … …Journal of Computer Science, Vol. 14, Issue 10 · 18 Oct 2018 · 7,326 accessesView PDFCite
Research ArticleOpen accessIn the abstractThe Optimal Implementation of a Generator of SinusoidSouhila Boudjema, Kaddour SaouchiThe embedded systems occupy a place increasingly important in our daily life. In recent years much of research it is focused on the miniaturization of the various electronic devices. In this study we present the architecture of a digital generator of frequency based on trigonometrically algorithm to obtain sample high frequencies. We treat a comparative study between various processors CORDIC: … …American Journal of Applied Sciences, Vol. 12, Issue 8 · 17 Sep 2015 · 6,292 accessesView PDFCite
Research ArticleOpen accessIn the abstractVHDL DESIGN AND HARDWARE REALIZATION OF HYBRIDARTIFICIAL INTELLIGENCE ARCHITECTURERajeswaran Nagalingam, Tenneti Madhu, Munagala SuryakalavathiEvolutionary Algorithms (EA) use Genetic Algorithm (GA) in many optimization problems to efficiently compute the function value in less time. In this study the weight optimization of the Artificial Neural Net-work (ANN), using the Back Propagation Network (BPN), is tested and presented with GA. The combined architecture of Neuro-Genetic (Hybrid Artificial Intelligence) approach is proposed and simulated results are provided … …American Journal of Applied Sciences, Vol. 11, Issue 5 · 24 Feb 2014 · 6,566 accessesView PDFCite
Research ArticleOpen accessIn the abstractALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETERR. M. Bommi, S. Selvakumar RajaIn the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full … …Journal of Computer Science, Vol. 10, Issue 7 · 12 Feb 2014 · 6,669 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite