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246 articles for “high speed”
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Research ArticleOpen accessPhrase in the titleIntegration of Human Factor in Design Ergonomics: Example of a High Speed Train Cabin DesignHajar El M’hadi, A. CherkaouiThe development of new technologies and technical progress has accelerated man/machine substitution. Work is disappearing in its human form. This technical progress has not avoided certain catastrophes occurring. These major disasters, both for man and for the environment, took place where reliability was at its highest level. The responsibility of the operator, of the human, the weak point in these … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 30 Mar 2017 · 7,888 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleDesign of a Low Power and High Speed Comparator using MUX based Full Adder Cell for Mobile CommunicationsG. Ramana Murthy, Ajay Kumar Singh, P. Velraj Kumar, Tan Wee Xin WilsonThis paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate … …American Journal of Applied Sciences, Vol. 14, Issue 1 · 16 Jan 2017 · 8,251 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleTowards an Integrated Intrusion Detection Monitoring in High Speed NetworksHassen SallayProblem statement: Security Management has become a critical aspect for large scale distributed systems. Particularly, recent Distributed Intrusion Detection Systems (DIDS) schemes in High Speed Networks (HSN) have raised new serious management problems and challenges. Increasing the effectiveness of IDS monitoring is primordial to satisfy the restrictive constraints in such large multi-domains environment for narrow context of HSN. Approach: We … …Journal of Computer Science, Vol. 7, Issue 7 · 30 Jun 2011 · 6,560 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleAnalysis of Jitter Impact on High Speed Transmissions of Wavelength-Division Multiplexing NetworksHazura Haroon, Hanim Abdul Razak, Sahbudin Shaari, P. Susthitha MenonIn this study, we conduct a thorough assessment of the effect of jitter occurrence in high speed 10 Gbps and 200 GHz Wavelength-Division Multiplexing (WDM) optical network. First, we present a simulation model to study the effect of jitter presence in the proposed network and then determine the maximum amount of jitter which the network can withstand. The model is … …American Journal of Applied Sciences, Vol. 11, Issue 12 · 13 Jan 2015 · 6,673 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleA RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESST. Yasodha, I. Jacob Raglend, K. Meena Alias JeyanthiA novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme … …American Journal of Applied Sciences, Vol. 11, Issue 6 · 29 Mar 2014 · 6,699 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETERR. M. Bommi, S. Selvakumar RajaIn the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full … …Journal of Computer Science, Vol. 10, Issue 7 · 12 Feb 2014 · 6,669 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleHARDWARE REALIZATION OF HIGH SPEED ELLIPTIC CURVE POINT MULTIPLICATION USING PRECOMPUTATION OVER GF(P)N. Shylashree, V. SridharTwo new theoretical approaches for the hardware realization of high speed elliptic curve point multiplication over a prime field (GF(p)) are presented. These hardware implementations use multiple units of elliptic curve point doublers, point adders and multiplexers. The modular hardware approach used here provides high speed and scalability. …Journal of Computer Science, Vol. 10, Issue 7 · 4 Feb 2014 · 6,611 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,481 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDFCite
Research ArticleOpen accessPhrase in the titleA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,078 accessesView PDFCite