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7 results for “Verilog HDL”
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Research ArticleOpen accessIn the keywordsOn-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform ArchitectureYazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman et al.Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 30 Nov 2010 · 8,010 accessesView PDFCite
Research ArticleOpen accessIn the abstractA NOVEL SUBSTITUTION BOX DESIGN FOR HUMMING BIRD-2 AGAINST SIDE CHANNEL ATTACKT. Blesslin Sheeba, P. RangarajanThe side-channel attacks are one of the effortless and commanding attacks against cryptographic implementation and their intention vary from protocols, modules, primitives and system. As a result of this attack, a serious threat to the security of cryptographic module was encountered. In effect, realization of the cryptographic algorithm has to take some countermeasure to resist against this type of attacks. … …Journal of Computer Science, Vol. 10, Issue 9 · 23 Apr 2014 · 6,590 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate ArrayMuhammad Ibn Ibrahimy, Rezwanul Ahsan, Iksannurazmi Bambang SoerosoThere are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 28 May 2013 · 6,512 accessesView PDFCite
Research ArticleOpen accessIn the abstractVLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless ReceiversRozita Teymourzadeh, Yazan Samir Algnabi, Masuri Othman et al.Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 4 · 5 Nov 2010 · 7,815 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,443 accessesView PDFCite
Research ArticleOpen accessIn the abstractIF-THEN Adder Application in Online DALUT ImplementationMohamed Al Mahdi Eshtawie, Masuri OthmanThis paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage … …American Journal of Applied Sciences, Vol. 4, Issue 9 · 30 Sep 2007 · 6,938 accessesView PDFCite