Research ArticleOpen accessIn the keywordsA PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTINGG. Nallathambi, S. RajaramThis study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect … …Journal of Mathematics and Statistics, Vol. 10, Issue 1 · 1 Feb 2014 · 6,741 accessesView PDFCite
Research ArticleOpen accessIn the abstractFramework for Managing the Very Large Scale Integration Design ProcessSabah Al-Fedaghi, Eman Al-DwaisanProblem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as … …American Journal of Applied Sciences, Vol. 9, Issue 2 · 13 Dec 2011 · 7,491 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordAN EFFICIENT CELL PLACEMENT USING GRAVITATIONAL SEARCH ALGORITHMSRose Al Qasem, Taisir EldosIn modern chip design, cell placement is a stage in which cells representing well-defined functions are assigned physical locations, in a way that optimizes the total area and routing length. Cell placement is an NP-complete problem and the exact solution is generally far from reach for a practically sized instance. Hence, diversified heuristic algorithms are used to solve this problem. … …Journal of Computer Science, Vol. 9, Issue 8 · 25 Jun 2013 · 7,371 accessesView PDFCite