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Research ArticleOpen accessIn the keywordsExploring Optimal Topology and Routing Algorithm for 3D Network on ChipN. Viswanathan, K. Paramasivam, K. SomasundaramProblem statement: Network on Chip (NoC) is an appropriate candidate to implement interconnections in SoCs. Increase in number of IP blocks in 2D NoC will lead to increase in chip area, global interconnect, length of the communication channel, number of hops transversed by a packet, latency and difficulty in clock distribution. 3D NoC is evolved to overcome the drawbacks of … …American Journal of Applied Sciences, Vol. 9, Issue 3 · 12 Jan 2012 · 7,190 accessesView PDF Cite

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