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35 results for “TI DSP”
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Research ArticleOpen accessEvery word in the titleDsPIC Based Power Assisted Steering Using Brushless Direct Current MotorG. R.P. Lakshmi, S. ParamasivamThis study illustrates the Electrically Assisted power Steering (EAS) using BLDC motor for a vehicle. Earlier the Electrically Assisted power Steering (EAS) was implemented with DSP. This study shows the usage of a dsPIC to control the BLDC motor with an encoder. The BLDC motor here is driven by dsPIC through a three phase inverter system. IRAMS type of inverter … …American Journal of Applied Sciences, Vol. 10, Issue 11 · 26 Sep 2013 · 6,751 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Novel Reconfigurable Execution Core for Merged DSP MicrocontrollerA. K. Rath, P. K. MeherThe study presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The proposed core can be connected to port 1 of Intel 8051 … …Journal of Computer Science, Vol. 3, Issue 10 · 31 Oct 2007 · 6,483 accessesView PDFCite
Research ArticleOpen accessEvery word in the titlePower Consumption and Performance’s Library on DSPs: Case Study MPEG2Jalel Ktari, Mohamed Abid, Nathalie Julien, Johann LaurentThe growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area, but also on power throughout the design space exploration. This article presents a high-level design space exploration methodology. It allows … …Journal of Computer Science, Vol. 3, Issue 3 · 31 Mar 2007 · 6,827 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of a Merged DSP Microcontroller for Embedded Systems using Discrete Orthogonal TransformA. K. Rath, P. K. MeherIn this paper we have proposed the design of a DSP microcontroller where the processor load is significantly reduced by relegating the math-intensive DSP algorithm to dedicated transform computing modules. It is shown that the use of such transform modules will facilitate scalability, reusability and flexibility for implementation of wide varieties of DSP functionalities. Moreover, it would be possible to … …Journal of Computer Science, Vol. 2, Issue 5 · 31 Aug 2006 · 6,918 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Low Cost Design Solution - DSP Based Active Power Factor Corrector for SMPS/ UPS( Single Phase)Samia Pillai Pitchai, B. UmamaheswariAs per international agency regulation (IEC 1000-3-2/EN 61000-3-2) and market expectation, it is important to reduce current harmonics in the AC line current drawn by SMPS/ UPS connected to AC Mains as source and also it is desired by the user to deliver maximum power output by achieving unity power factor. To achieve the above objectives in SMPS/ UPS, APFC … …American Journal of Applied Sciences, Vol. 3, Issue 1 · 31 Jan 2006 · 6,896 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDSP-128:Stream Cipher Based On Discrete Log Problem And Polynomial ArithmeticKhaled M. Suwais, Azman SamsudinDSP-128 is a new multithreaded stream cipher based on the intractability of the Discrete Logarithm Problem (DLP) with key size of 128-bit. The design of DSP-128 is divided into three stages: Initialization Stage, Keystream Generation Stage, and Encryption Stage. The design goal of DSP-128 is to come up with a secure stream cipher with good performance for data encryption. The … …American Journal of Applied Sciences, Vol. 5, Issue 7 · 31 Jul 2008 · 7,396 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleANN Based DSPIC Controller for Reactive Power CompensationR.A. Jayabarathi, N.B. DevarajanIn India with a power shortage of about 10% of installed capacity, the transmission and distribution losses are relatively high. One of the reasons for the large loss is the excessive reactive loads on the primary distribution feeder. With the right amount of reactive power compensation, as system load varies, line losses can be considerably reduced. The application of Artificial … …American Journal of Applied Sciences, Vol. 4, Issue 7 · 31 Jul 2007 · 6,851 accessesView PDFCite
Research ArticleOpen accessIn the keywordsImpact of the Use of Object Request Broker Middleware for Inter-Component Communications in C6416 Digital Signal Processor Based Software Communications Architecture Radio SystemsWael A. Murtada, Mohamed M. Zahra, Magdi Fikri et al.Problem statement: This study presents an in-depth analysis of the performance of Software Communications Architecture (SCA) component-based waveform applications in terms of inter-component communications. The main limitation with SCA, in the context of embedded systems, is the additional cost introduced by the use of Object Request Broker (ORB) middleware. The ORB middleware handles the interaction between components and objects in … …Journal of Computer Science, Vol. 8, Issue 6 · 3 Apr 2012 · 7,239 accessesView PDFCite
Research ArticleOpen accessIn the keywordsField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBraun's Multipliers: Spartan-3AN based Design and ImplementationMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The … …Journal of Computer Science, Vol. 7, Issue 11 · 18 Aug 2011 · 6,909 accessesView PDFCite