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28 results for “Processor Architecture”
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Research ArticleOpen accessEvery word in the titleA Novel Method to Predict Processor Performance by Modeling Different Architecture ParametersJoseph IssaPredicting processor throughput and performance is one of the essential aspects of computer architecture. It is crucial to model processor performance behavior for future architectures based on the existing data set. Modeling processor performance for a given workload enables architects to enhance processor features to meet specific performance targets for a given benchmark. Developing an estimation method to predict performance … …Journal of Computer Science, Vol. 16, Issue 4 · 22 Apr 2020 · 7,317 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleImpact of the Use of Object Request Broker Middleware for Inter-Component Communications in C6416 Digital Signal Processor Based Software Communications Architecture Radio SystemsWael A. Murtada, Mohamed M. Zahra, Magdi Fikri et al.Problem statement: This study presents an in-depth analysis of the performance of Software Communications Architecture (SCA) component-based waveform applications in terms of inter-component communications. The main limitation with SCA, in the context of embedded systems, is the additional cost introduced by the use of Object Request Broker (ORB) middleware. The ORB middleware handles the interaction between components and objects in … …Journal of Computer Science, Vol. 8, Issue 6 · 3 Apr 2012 · 7,239 accessesView PDFCite
Research ArticleOpen accessIn the keywordsLOW COMPLEXITY CONSTRAINTS FOR ENERGY AND PERFORMANCE MANAGEMENT OF HETEROGENEOUS MULTICORE PROCESSORS USING DYNAMIC OPTIMIZATIONA. S. Radhamani, E. BaburajOptimization in multicore processor environment is significant in real world dynamic applications, as it is crucial to find and track the change effectively over time, which requires an optimization algorithm. In massively parallel processing multicore processor architectures, like other population based metaheuristics Constraint based Bacterial Foraging Particle Swarm Optimization (CBFPSO) scheduling can be effectively implemented. In this study we discuss … …Journal of Computer Science, Vol. 10, Issue 8 · 3 Apr 2014 · 6,645 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of a Merged DSP Microcontroller for Embedded Systems using Discrete Orthogonal TransformA. K. Rath, P. K. MeherIn this paper we have proposed the design of a DSP microcontroller where the processor load is significantly reduced by relegating the math-intensive DSP algorithm to dedicated transform computing modules. It is shown that the use of such transform modules will facilitate scalability, reusability and flexibility for implementation of wide varieties of DSP functionalities. Moreover, it would be possible to … …Journal of Computer Science, Vol. 2, Issue 5 · 31 Aug 2006 · 6,918 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel Reconfigurable Execution Core for Merged DSP MicrocontrollerA. K. Rath, P. K. MeherThe study presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The proposed core can be connected to port 1 of Intel 8051 … …Journal of Computer Science, Vol. 3, Issue 10 · 31 Oct 2007 · 6,483 accessesView PDFCite
Research ArticleOpen accessIn the keywordsTeaching Computer Organization and Architecture Using Simulation and FPGA ApplicationsKasim M. Al-AubidyThis paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has … …Journal of Computer Science, Vol. 3, Issue 8 · 31 Aug 2007 · 7,100 accessesView PDFCite
Research ArticleOpen accessIn the abstractBased Approach to Improve the All-Pair Shortest Path ComputationLau Nguyen Dinh, Le Thanh TuanThis paper presents the development of a centralized algorithm for finding the shortest path between all pairs of vertices on a graph, utilizing the basic structure of the Floyd-Warshall sequential algorithm. The proposed algorithm leverages multiple processors to compute the shortest path between all vertex pairs, with one processor taking the central role in data management. This central processor divides … …Journal of Computer Science, Vol. 21, Issue 7 · 30 Jun 2025 · 2,903 accessesView PDFCite
Research ArticleOpen accessIn the abstractThe Effect of RSA Exponential Key Growth on the Multi-Core Computational ResourceMohamad A. Mohamed, Ammar Y. Tuama, Mokhairi Makhtar et al.Cryptography has been widely used as a mean to secure message communication. A cryptosystem is made up of a publicly available algorithm and a secretly kept key. The algorithm is responsible for transforming the original message into something unintelligible. The result of losing the key or cracked algorithm can be catastrophic, where all secret communications will be known to adversaries. … …American Journal of Engineering and Applied Sciences, Vol. 9, Issue 4 · 25 Nov 2016 · 7,827 accessesView PDFCite
Research ArticleOpen accessIn the abstractAndroid Based Energy Aware Framework for Porting Legacy ApplicationsNaeem Zafar AzeemiTrend is growing towards using complex multimedia functions on smaller devices. In this study, we explore the effect of migrating legacy signal processing software applications algorithms from large form factor devices to the smaller one such as handheld mobile devices known as Energy Conscious Mobile Computing Systems (EConMCS). We concentrate on Source Code Volatility (SCV), including inherent algorithm complexity and … …American Journal of Applied Sciences, Vol. 11, Issue 12 · 3 Jan 2015 · 6,288 accessesView PDFCite
Research ArticleOpen accessIn the abstractHIT RATE MAXIMIZATION BY LOGICAL CACHE PARTITIONING IN A MULTI-CORE ENVIRONMENTS. Muthukumar, P. K. JawaharIt is imperative for any level of cache memory in a multi-core architecture to have a well defined, dynamic replacement algorithm in place to ensure consistent superlative performance. The most prevalently used LRU replacement policy does not acquaint itself dynamically to the changes in the workload. As a result, it can lead to sub-optimal performance for certain applications whose workloads … …Journal of Computer Science, Vol. 10, Issue 3 · 29 Nov 2013 · 6,283 accessesView PDFCite