9 articles for “Power Delay Product”

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Research ArticleOpen accessIn the keywordsUltra Low Power Single Edge Triggered Delay Flip Flop Based Shift Registers Using 10-Nanometer Carbon Nano Tube Field Effect TransistorRavi Thiyagarajan, Kannan VeerappanCarbon Nano Tube Field Effect Transistor is currently considered as promising successor of Metal Oxide Semiconductor Field Effect Transistor. The scaling down of the Metal Oxide Semiconductor device faced serious limits like short channel effect, tunnelling through gate oxide layer, associated leakage currents and power dissipation when its dimension shrink down to 22 nanometer range. Further scaling of Metal Oxide … …American Journal of Applied Sciences, Vol. 10, Issue 12 · 14 Oct 2013 · 6,749 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsDesign of an Error Tolerant AdderA. N. Jayanthi, C. S. RavichandranProblem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 13 Mar 2012 · 7,249 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,481 accessesView PDF Cite

Research ArticleOpen accessIn the abstractLow Power Multiplier by Effective Capacitance ReductionNageshwar Reddy Peddamgari, Damu RadhakrishnanIn this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the … …American Journal of Engineering and Applied Sciences, Vol. 10, Issue 1 · 22 Feb 2017 · 7,462 accessesView PDF Cite

Research ArticleOpen accessIn the abstractUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,612 accessesView PDF Cite

EditorialOpen accessIn the abstractON THE CHALLENGES OF THE USE AND INTEGRATION OF RENEWABLE ENERGY SOURCESMariano MartínOverview: Although renewable energy sources are plentiful, their availability is highly volatile in time and distributed across regions while and the processes that transform them into useful power or chemicals are underdeveloped. In this work we discuss on the scope for the use and integration of renewable energy sources and the future development of the alternatives. Energy, the sources and … …Energy Research Journal, Vol. 5, Issue 1 · 11 Sep 2014 · 7,540 accessesView PDF Cite

Research ArticleOpen accessIn the abstractVLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based on High Speed Carry Select AdderS. Karunakaran, N. KasthuriRecent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 5 Jan 2013 · 7,179 accessesView PDF Cite

Research ArticleOpen accessIn the abstractDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,155 accessesView PDF Cite

Research ArticleOpen accessAll words, across the recordVoltage Sag Effects on the Process Continuity of a Refinery with Induction Motors LoadsTarek I. ElShennawy, Mahmoud A. El-Gammal, Amr Y. Abou-GhazalaProblem statement: Process continuity of industrial plants (like a refinery) is subjected to several shutdowns due to voltage sags causing large induction motors to trip, either by undervoltage or by overcurrent relays, sometimes by the mechanical protection. These unplanned shutdowns cost the plant tens of thousands of dollars per shutdown in addition to material damage costs, restart charges and any … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,120 accessesView PDF Cite