Research ArticleOpen accessIn the keywordsDelay and Power Reduction in New Routing FabricsS. Vijayakumar, J. Sundararajan, P. Kumar, K. NithyaIn this study we created a new routing fabric for reducing power and delay. The power consumed in a FPGA core consists of both static and dynamic components. Static power contributes only 10% of the total power consumed in a FPGA. On the other hand, dynamic power contributes over 90% of the total power consumed and it is the main … …American Journal of Applied Sciences, Vol. 10, Issue 12 · 23 Oct 2013 · 6,449 accessesView PDFCite
Research ArticleOpen accessIn the abstractHUNTING PERNICIOUS ATTACKS IN WEB APPLICATIONS WITH XPROBERR. Suguna, T. Kujani, N. Suganya, C. KrishnaveniNowadays internet is loaded with tons of innovative web applications. This instantaneous growth has paved way for a number of security exposures. Cross Site Scripting attacks (XSS), SQL Injection (SQLI) and Malicious File Execution (MFE) are the foremost web related vulnerabilities reported by Open Web Application Security Project (OWASP). The attackers take advantage of the vulnerabilities in the code of … …American Journal of Applied Sciences, Vol. 11, Issue 7 · 2 May 2014 · 6,859 accessesView PDFCite
Research ArticleOpen accessIn the abstractHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,481 accessesView PDFCite