6 articles for “Full Adder”

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Research ArticleOpen accessPhrase in the titleDesign of a Low Power and High Speed Comparator using MUX based Full Adder Cell for Mobile CommunicationsG. Ramana Murthy, Ajay Kumar Singh, P. Velraj Kumar, Tan Wee Xin WilsonThis paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate … …American Journal of Applied Sciences, Vol. 14, Issue 1 · 16 Jan 2017 · 8,251 accessesView PDF Cite

Research ArticleOpen accessPhrase in the titleALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETERR. M. Bommi, S. Selvakumar RajaIn the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full … …Journal of Computer Science, Vol. 10, Issue 7 · 12 Feb 2014 · 6,669 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsGate Replacement Technique for Reducing Leakage Current in Wallace Tree MultiplierNaveen Raman, ThanushkodiLeakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace … …Journal of Computer Science, Vol. 9, Issue 2 · 30 Mar 2013 · 6,763 accessesView PDF Cite

Research ArticleOpen accessIn the keywordsA Novel Reversible BCD Adder For Nanotechnology Based SystemsMajid Haghparast, Keivan NaviThis paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as &#34Copying Circuit&#34 to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all … …American Journal of Applied Sciences, Vol. 5, Issue 3 · 31 Mar 2008 · 10,135 accessesView PDF Cite

Research ArticleOpen accessIn the abstractA Novel Fault-Tolerant Majority Gate Architecture for Robust Operation in QCA-Based Nano CircuitsAmi Patel, Vrushank Shah, Dipti KhurgeQuantum Dot Cellular Automata (QCA) is one of the promising alternatives to the traditional CMOS technologies for next-generation nanocomputing, which can be integrated at a higher density and has a higher possibility of low power consumption. Fabrication defects, environmental noise, and fault tolerance, especially in larger circuits, are challenging for practical implementation of QCA circuits. A new Fault-Tolerant Majority Gate … …Journal of Computer Science, Vol. 22, Issue 7 · 7 Jul 2026 · 1,194 accessesView PDF Cite

Research ArticleOpen accessIn the abstractDesign and Analysis of Adders using Nanotechnology Based Quantum dot Cellular AutomataS. Karthigai Lakshmi, G. AthishaProblem statement: The area and complexity are the major issues in circuit design. Here, we propose different types of adder designs based on Quantum dot Cellular Automata (QCA) that reduces number of QCA cells and area compare to previous designs. The quantum dot cellular automata is a novel computing paradigm in nanotechnology that can implement digital circuits with faster speed, … …Journal of Computer Science, Vol. 7, Issue 7 · 30 Jun 2011 · 7,311 accessesView PDF Cite