Research ArticleOpen accessIn the keywordsDesign of 8-4 and 9-4 Compressors Forhigh Speed MultiplicationR. Marimuthu, Dhruv Bansal, S. Balamurugan, P. S. MallickThis study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order … …American Journal of Applied Sciences, Vol. 10, Issue 8 · 24 Jul 2013 · 7,213 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,078 accessesView PDFCite
Research ArticleOpen accessIn the abstractA New Efficient-Silicon Area MDAC SynapseZied Gafsi, Nejib Hassen, Mongia Mhiri, Kamel BesbesUsing the binary representation ΣiDi2i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named … …American Journal of Applied Sciences, Vol. 4, Issue 6 · 30 Jun 2007 · 7,158 accessesView PDFCite
Research ArticleOpen accessIn the abstractUltra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold RegimePriya Gupta, Anu Gupta, Abhijit AsatiThe computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission … …American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4 · 17 Nov 2015 · 8,612 accessesView PDFCite
Research ArticleOpen accessAll words, across the recordA Bit-Serial Multiplier Architecture for Finite Fields Over Galois FieldsHero Modares, Yasser Salem, Rosli Salleh, Majid Talebi ShahgoliProblem statement: A fundamental building block for digital communication is the Public-key cryptography systems. Public-Key Cryptography (PKC) systems can be used to provide secure communications over insecure channels without exchanging a secret key. Implementing Public-Key cryptography systems is a challenge for most application platforms when several factors have to be considered in selecting the implementation platform. Approach: The most popular … …Journal of Computer Science, Vol. 6, Issue 11 · 23 Oct 2010 · 8,431 accessesView PDFCite