Literature ReviewOpen accessIn the keywordsSurvey and Comparison of Operating Concept for Routing Protocols in DTNKawakib K. Ahmed, Mohd Hasbullah Omar, Suhaidi HassanDelay Tolerant Network (DTN) are promising techniques to enable data transmission in challenging scenarios where sophisticated infrastructure is not available and the end-to-end path does not exist at the moment of data transmission. These networks are characterized by a long delay, intermittent connectivity and high error rates. Furthermore, the dynamic topology of the network may change randomly. Therefore, routing is … …Journal of Computer Science, Vol. 12, Issue 3 · 23 Apr 2016 · 7,362 accessesView PDFCite
Research ArticleOpen accessIn the keywordsEfficient Scheduling of Packets in Wireless Sensor Networks Using Priority Based Scheduling ApproachB. Booba, T.V. GopalThe packet scheduling is essential and plays an important role to sense the element nodes with resource constraints in Wireless Networks. The packet scheduling scheme also scale the energy consumption and end-to-end information transmission delay in time period and non-real-time information packets during wireless transmission. The proposed Priority based Packet Scheduling (PPS) technique has a tendency to overcome the issues … …Journal of Computer Science, Vol. 11, Issue 1 · 9 Aug 2014 · 7,091 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDESIGN OF HIGH-SPEED PARALLEL IN PARALLEL OUT SHIFT REGISTER USING ALGAAS/GAAS MODFET TECHNOLOGYV. Ganesan, K. S. ShajiThis study enumerates the efficient design and analysis of Parallel In Parallel Out (PIPO) shift register using AlGaAs/GaAs MODFET D Flip-flop. The transient and power analysis are obtained with operating voltage at 1.3 V for the D flip-flop and PIPO shift register using pspice tool. There are many issues facing while integrating many number of transistors like delay, power dissipation, … …American Journal of Applied Sciences, Vol. 11, Issue 8 · 8 May 2014 · 7,146 accessesView PDFCite
Research ArticleOpen accessIn the keywordsHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,481 accessesView PDFCite
Research ArticleOpen accessIn the keywordsIMPROVING THE PERFORMANCE AND REDUCING BIT ERROR RATE ON WIRELESS DEEP FADING ENVIRONMENT RECEIVERSK. Jayanthi, V. P. Arunachalam, C. VasanthanayakiOne of the major challenges in wireless communication system is increasing complexity and reducing performance in detecting the received digital information in indoor and outdoor Environments. Consequently to overcome this problem we analyze the delay performance of a multiuser with perfect channel state information transmitting data on deep fading environment. In this proposed system, the Wireless Deep Fading Environment (WDFE) … …Journal of Computer Science, Vol. 10, Issue 3 · 29 Nov 2013 · 7,100 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of 8-4 and 9-4 Compressors Forhigh Speed MultiplicationR. Marimuthu, Dhruv Bansal, S. Balamurugan, P. S. MallickThis study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order … …American Journal of Applied Sciences, Vol. 10, Issue 8 · 24 Jul 2013 · 7,213 accessesView PDFCite
Research ArticleOpen accessIn the keywordsNEW BURST ASSEMBLY AND SCHEDULING TECHNIQUE FOR OPTICAL BURST SWITCHING NETWORKSV. Kavitha, V. PalanisamyThe Optical Burst Switching is a new switching technology that efficiently utilizes the bandwidth in the optical layer. The key areas to be concentrated in Optical Burst Switching (OBS) networks are the burst assembly and burst scheduling i.e., assignment of wavelengths to the incoming bursts. This study presents a New Burst Assembly and Scheduling (NBAS) technique in a simultaneous multipath … …Journal of Computer Science, Vol. 9, Issue 8 · 6 Jul 2013 · 6,944 accessesView PDFCite
Research ArticleOpen accessIn the keywordsMultichannel Cognitive Cross Layer Optimization for Improved Video TransmissionMeenakshi Murugappan, Manimekalai Thirunavukkarasu, Maneesha S. MohanMultimedia applications particularly real-time video transmission in wireless networks, envisions end to end user perceived video quality as an important QoS parameter to be achieved. Cognitive Radio promising efficient spectrum utilization combined with Cross layer optimization is seen as a powerful combination to achieve the desired video quality. This study proposes Optimal Channel Sensed Multichannel Cognitive MAC (OCSM-CMAC), a QoS … …Journal of Computer Science, Vol. 9, Issue 1 · 6 Feb 2013 · 7,199 accessesView PDFCite
Research ArticleOpen accessIn the keywordsCluster Based Data Consistency for Cooperative Caching over Partitionable Mobile Adhoc NetworkP. Kuppusamy, B. KalaavathiProblem statement: Data availability and consistency are foremost issues in Mobile Ad hoc Networks due to the absence of permanent infrastructure. Cooperative caching addresses the data availability issue through coordinating the mobile nodes and sharing the cache copies among them. In the meantime, the mobile node must ensure the staleness of cache copies. The consistency maintenance resolves the staleness of … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 10 Jul 2012 · 6,853 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of an Error Tolerant AdderA. N. Jayanthi, C. S. RavichandranProblem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 13 Mar 2012 · 7,249 accessesView PDFCite