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232 articles for “Low Power”
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Research ArticleOpen accessEvery word in the titleA Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection RatioIsmail Nabhan, Moussa AbdallahProblem statement: High speed operational amplifier is always an on-going research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0.5 μm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure stability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,241 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCSBakoune Pierre Hypolite, Wembe Tafo Evariste, Moukengue Imano AdolpheThis paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results … …American Journal of Engineering and Applied Sciences, Vol. 12, Issue 2 · 6 May 2019 · 7,677 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,159 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleDesign of a Single-Phase Rectifier with Improved Power Factor and Low THD using Boost Converter TechniqueIsmail Daut, Rosnazri Ali, Soib TaibThe method of using Boost type of converter was proposed for a 300W single-phase rectifier in this paper. By designing the necessary techniques and methodology, the overall Power Factor (PF) and Total Harmonic Distortion would be improved to the expectation. The cause of having low PF and high THD for a diode-capacitor type of rectifiers is related to non-linearity of … …American Journal of Applied Sciences, Vol. 3, Issue 9 · 30 Sep 2006 · 7,132 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Low Cost Design Solution - DSP Based Active Power Factor Corrector for SMPS/ UPS( Single Phase)Samia Pillai Pitchai, B. UmamaheswariAs per international agency regulation (IEC 1000-3-2/EN 61000-3-2) and market expectation, it is important to reduce current harmonics in the AC line current drawn by SMPS/ UPS connected to AC Mains as source and also it is desired by the user to deliver maximum power output by achieving unity power factor. To achieve the above objectives in SMPS/ UPS, APFC … …American Journal of Applied Sciences, Vol. 3, Issue 1 · 31 Jan 2006 · 6,899 accessesView PDFCite
Research ArticleOpen accessEvery word in the titlePeak to Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing System with a Significant Low ComplexityMahamod Ismail, J. S. Mandeep, Montadar Abas Taher, M. T. IslamThe Orthogonal Frequency Division Multiplexing (OFDM) has been widely used in many applications in the last decade. It provides good benefits compared to the single carrier systems. However, it has a bad property represented by the high-output Peak to Average Power Ratio (PAPR) which is considered as its major problem. There are many techniques to reduce the PAPR values such … …American Journal of Applied Sciences, Vol. 9, Issue 12 · 20 Dec 2012 · 6,594 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBit Error Rate Analysis of RS (7, 3) Coded Frequency Shift Keying Using SimulinkT.A. Shanmugasundaram, V. VijayabaskarBit Error Rate is an essential parameter to quantize the effectiveness of transceiver circuits used in low power, low duty cycle sensor nodes. BER can figure out their performance in terms of number of retransmissions, which keeps the node to consume its battery power undesirably rather than conserving it. Forward Error Correction schemes ensure the transceiver circuit to effectively perform … …American Journal of Applied Sciences, Vol. 12, Issue 2 · 25 Mar 2015 · 7,051 accessesView PDFCite
Research ArticleOpen accessIn the keywordsHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,487 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDESIGN OF OPTIMAL CARRY SKIP ADDER AND CARRY SKIP BCD ADDER USING REVERSIBLE LOGIC GATESPraveena Murugesan, Thanushkodi KeppanagounderReversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate … …Journal of Computer Science, Vol. 10, Issue 5 · 26 Dec 2013 · 6,683 accessesView PDFCite
Research ArticleOpen accessIn the keywordsBER Performance and Data Throughput of Sinusoidal Template-Based Impulse-Radio Ultra Wideband Receivers for Wireless Body Area NetworksMohamad Abou El-Nasr, Heba ShabanWindowed sinusoidal template-based correlator receivers are good candidates for high-data rate low-power Ultra Wideband (UWB) systems. Their performance approaches the performance of optimal detectors and provides low-power consumption. However, the ultra short pulses of UWB technology makes it sensitive to timing-errors. In this paper, the Bit-Error-Rate (BER) performance and maximum allowable data throughput of Equally-Correlated Pulse Position Modulation (EC-PPM) modulation … …American Journal of Applied Sciences, Vol. 10, Issue 5 · 30 May 2013 · 6,507 accessesView PDFCite