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198 results for “Hardware”
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Research ArticleOpen accessEvery word in the titleA Single Core Hardware Module of a Data Compression Scheme Using Prediction by Partial Matching TechniqueJubayer Jalil, Md. Mamun, Mohd. Marufuzzaman, Hafizah HusainProblem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,255 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleSubway Train Braking System: A Fuzzy Based Hardware ApproachMamun Bin Ibne Reaz, Jubayer Jalil, Hafizah Husain, Badariah BaisProblem statement: Automated subway train-braking system require perfection, efficiency and fast response. In order to cope with this concerns, an appropriate algorithm need to be developed which need to be implemented in hardware for faster response. Approach: In this research, the FPGA realization of fuzzy based subway train braking system has been presented on an Alter FLEX10K device to provide … …American Journal of Applied Sciences, Vol. 8, Issue 7 · 24 Jun 2011 · 7,175 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleSingle Core Hardware Module to Implement Partial Encryption of Compressed ImageMamun Bin Ibne Reaz, Md. Syedul Amin, Fazida Hanim Hashim, Khandaker AsaduzzamanProblem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that … …American Journal of Applied Sciences, Vol. 8, Issue 6 · 13 Jun 2011 · 7,379 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA DevicesMuhammad H. RaisProblem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,334 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleReconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)Mohamed Abdelkader Bencherif, Hamid Bessalah, Abderrezak GuessoumProblem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,346 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleComparative Performance Study of Improved Heap Sort Algorithm on Different HardwareVandana Sharma, Satwinder Singh, K. S. KahlonProblem statement: Several efficient algorithms were developed to cope with the popular task of sorting. Improved heap sort is a new variant of heap sort. Basic idea of new algorithm is similar to classical Heap sort algorithm but it builds heap in another way. The improved heap sort algorithm requires nlogn-0.788928n comparisons for worst case and nlogn-n comparisons in average … …Journal of Computer Science, Vol. 5, Issue 7 · 31 Jul 2009 · 6,824 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleA Control-Oriented Coverage Metric and its Evaluation for Hardware DesignsShireesh Verma, Kiran Ramineni, Ian G. HarrisProblem statement: Dynamic verification, the use of simulation to determine design correctness, is widely used due to its tractability for large hardware designs. A serious limitation of dynamic techniques is the difficulty in determining whether or not a test sequence is sufficient to detect all likely design errors. Coverage metrics are used to address this problem by providing a set … …Journal of Computer Science, Vol. 5, Issue 4 · 30 Apr 2009 · 7,528 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleEfficient Reversible Montgomery Multiplier and Its Application to Hardware CryptographyNoor Muhammed Nayeem, Lafifa Jamal, Hafiz Md. Hasan BabuProblem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not … …Journal of Computer Science, Vol. 5, Issue 1 · 31 Jan 2009 · 7,852 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHardware Implementation of Higher Throughput Anti-Collision Algorithm for Radio Frequency Identification SystemJahariah Sampe, Masuri OthmanThis paper presents a proposed hardware implementation of Higher Throughput Anti-Collision Algorithm (HTACA) for Radio Frequency Identification (RFID) system. Our proposed HTACA combines a pipeline and a deterministic anti-collision technique in order to enhance its performances. These downlink and uplink operations are concurrently executed during the identification process. The downlink operation is purposely pre-selected a group of tags base on … …American Journal of Engineering and Applied Sciences, Vol. 1, Issue 2 · 30 Jun 2008 · 7,443 accessesView PDFCite