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62 results for “FPGA”
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Research ArticleOpen accessIn the keywordsDESIGN AND IMPLEMENTATION OF GLOBAL POSITIONING SYSTEM RECEIVER IN FIELD PROGRAMMABLE GATE ARRAY WITH SHORT MESSAGE SERVICEGovindaraju Kavya, Vittal Thulasi BaiIn recent years, survival rate from myocardial infarction and bundle branch block has been increased due to the advancements in medical field. Continuous monitoring and location management of these patients becomes an essential task. Hence this study aims in design and development of GPS in a Field Programmable Gate Array (FPGA) and interfaced with a GSM modem to transmit the … …Journal of Computer Science, Vol. 10, Issue 1 · 12 Nov 2013 · 7,563 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel Architecture of Maximum Power Point Tracking for Ultra-Low-Power Based Hybrid Energy Harvester in Ubiquitous Devices: A ReviewMichelle Lim Sern Mi, Sawal Hamid Muhammad Ali, Md Shabiul IslamThis research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 7,155 accessesView PDFCite
Research ArticleOpen accessIn the keywordsField Programmable Gate Array Based RF-THI Pulse Width Modulation Control for Three Phase Nverter Using Matlab Modelsim CosimulationValantina Stephen, L. Padma Suresh, P. MuthukumarThis study proposes different configurations of PWM techniques for harmonic reduction and improvement of fundamental peak voltage. For providing adjustable frequency power to industrial applications, three-phase inverter is preferred. The general aim of this study is to reduce the third order harmonics and improve the Harmonic Spread Factor by different PWM techniques using matlab modelsim cosimulation. The gating signals to … …American Journal of Applied Sciences, Vol. 9, Issue 11 · 1 Sep 2012 · 7,443 accessesView PDFCite
Research ArticleOpen accessIn the keywordsReconfigurable Hardware Architecture for Network Intrusion Detection SystemA. Kaleel Rahuman, G. AthishaIntrusion rule processing in reconfigurable hardware enables intrusion detection and prevention. The use of reconfigurable hardware for network security applications has great strides as Field Programmable Gate Array (FPGA) devices have provided larger and faster resources. This proposes architecture called “BV-TCAM” is presented, which is implemented for an FPGA-based Network Intrusion Detection Systems (NIDS). The BV-TCAM architecture combines the Ternary … …American Journal of Applied Sciences, Vol. 9, Issue 10 · 16 Aug 2012 · 6,981 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of Field Programmable Gate Array Based Emulators for Motor Control ApplicationsAhmed Ben Achballah, Slim Ben Othman, Slim Ben SaoudProblem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to … …American Journal of Applied Sciences, Vol. 9, Issue 8 · 12 Jun 2012 · 8,723 accessesView PDFCite
Research ArticleOpen accessIn the keywordsMulticore Based Open Loop Motor Controller Embedded System for Permanent Magnet Direct Current MotorK. Baskaran, K.S. Vijula GraceProblem statement: In an advanced electronics world most of the applications are developed by microcontroller based embedded system. Approach: Multicore processor based motor controller was presented to improve the processing speed of the controller and improve the efficiency of the motor by maintaining constant speed. It was based on the combination of Cortex processor (Software core) and Field Programmable Gate … …American Journal of Applied Sciences, Vol. 9, Issue 6 · 22 Mar 2012 · 7,035 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive ImplementationHedi Abdelkrim, Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben SaoudProblem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using … …American Journal of Engineering and Applied Sciences, Vol. 5, Issue 1 · 18 Feb 2012 · 8,978 accessesView PDFCite
Research ArticleOpen accessIn the keywordsField Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's MultipliersMuhammad H. Rais, Mohammed H. Al MijalliProblem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using … …Journal of Computer Science, Vol. 7, Issue 12 · 22 Oct 2011 · 6,677 accessesView PDFCite
Research ArticleOpen accessIn the keywordsSingle Core Hardware Module to Implement Boolean Function Classification TechniquesMohd. Marufuzzaman, Md. Mamun, Fazidah Hanim Hashim, Labonnah F. RahmanProblem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,408 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Single Core Hardware Module of a Data Compression Scheme Using Prediction by Partial Matching TechniqueJubayer Jalil, Md. Mamun, Mohd. Marufuzzaman, Hafizah HusainProblem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,255 accessesView PDFCite