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45 articles for “CMOS IC”
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Review ArticleOpen accessIn the abstractArchitecture of an Ultra-Low-Power Fully Autonomous Universal Power Conditioner of Energy Harvester for Wireless Sensor Networks: A ReviewYeo Kim Heng, Md. Shabiul Islam, Susthitha Menon et al.A fully autonomous Universal Power Conditioner (UPC) that can accept energy from any micro-energy harvester (e.g., photovoltaic, thermoelectric, electromagnetic, piezoelectric etc.) is proposed. Generally, UPC removes the need of multiple optimized source specific converters. But, the proposed UPC architecture will be Ultra-Low-Power (ULP) with maximized efficiency to support the low energy levels generated by harvesting sources. This UPC uses a … …American Journal of Applied Sciences, Vol. 13, Issue 3 · 28 Mar 2016 · 7,782 accessesView PDFCite
Review ArticleOpen accessIn the abstractArchitecture of Ultra Low Power Micro Energy Harvester Using RF Signal for Health Care Monitoring System: A ReviewFarah Fatin Zulkifli, Jahariah Sampe, Muhammad Shabiul Islam, Mohd Ambri MohamedThis research presents architecture of Ultra Low Power (ULP) Micro Energy Harvester (MEH) using Radio Frequency (RF) signal as an input. RF has many advantages compared to other ambient sources because it is not affected by changes of weather or time, does not require heat or wind exposure and it can be moved randomly within the bound of the transmission … …American Journal of Applied Sciences, Vol. 12, Issue 5 · 7 Jul 2015 · 6,956 accessesView PDFCite
Research ArticleOpen accessIn the abstractALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETERR. M. Bommi, S. Selvakumar RajaIn the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full … …Journal of Computer Science, Vol. 10, Issue 7 · 12 Feb 2014 · 6,669 accessesView PDFCite
Research ArticleOpen accessIn the abstractA PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTINGG. Nallathambi, S. RajaramThis study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect … …Journal of Mathematics and Statistics, Vol. 10, Issue 1 · 1 Feb 2014 · 6,741 accessesView PDFCite
Research ArticleOpen accessIn the abstractApplication Specific Integrated Circuits Design and Implementation of Rademacher and Walsh FunctionsA. Abbasi, A. R.M. Alamoud, S. A. AbbasiThe orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today’s DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell … …American Journal of Engineering and Applied Sciences, Vol. 6, Issue 4 · 7 Jan 2014 · 7,340 accessesView PDFCite
Research ArticleOpen accessIn the abstractAN IMPROVED DESIGN OF REVERSIBLE BINARY TO BINARY CODED DECIMAL CONVERTER FOR BINARY CODED DECIMAL MULTIPLICATIONPraveena Murugesan, Thanushkodi KeppanagounderReversible logic gates under ideal conditions produce zero power dissipation. This factor highlights the usage of these gates in optical computing, low power CMOS design, quantum optics and quantum computing. The growth of decimal arithmetic in various applications as stressed the need to propose the study on reversible binary to BCD converter which plays a greater role in decimal multiplication … …American Journal of Applied Sciences, Vol. 11, Issue 1 · 28 Nov 2013 · 7,510 accessesView PDFCite
Research ArticleOpen accessIn the abstractComparative Analysis of Reversible Logic Based Carbon Nano Tube Field Effect Transistor Multiplexer PerformanceY. Varthamanan, V. KannanThis study is about the design and analysis of a reversible logic based multiplexer, that is realized using carbon nano tube transistor. Reversible logic realization of the digital circuits offers numerous advantages over conventional circuit design. Power analysis was performed using HSPICE simulation software and the results are obtained for the 2×1 and 4×1 multiplexer transient behavior. The power consumption … …American Journal of Applied Sciences, Vol. 10, Issue 11 · 5 Oct 2013 · 6,637 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Architecture of Maximum Power Point Tracking for Ultra-Low-Power Based Hybrid Energy Harvester in Ubiquitous Devices: A ReviewMichelle Lim Sern Mi, Sawal Hamid Muhammad Ali, Md Shabiul IslamThis research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome … …American Journal of Applied Sciences, Vol. 10, Issue 10 · 6 Sep 2013 · 7,155 accessesView PDFCite
Research ArticleOpen accessIn the abstractA Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance SchemeUma Ramadass, Krishnappriya, Jebashini Ponnian, P. DhavachelvanIn this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model … …American Journal of Applied Sciences, Vol. 10, Issue 8 · 24 Jul 2013 · 7,045 accessesView PDFCite
Research ArticleOpen accessIn the abstractGate Replacement Technique for Reducing Leakage Current in Wallace Tree MultiplierNaveen Raman, ThanushkodiLeakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace … …Journal of Computer Science, Vol. 9, Issue 2 · 30 Mar 2013 · 6,763 accessesView PDFCite