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23 results for “digital circuit design”
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Research ArticleOpen accessIn the abstractModelling of Digital Assisted Backend Correction Analogue to Digital Converters with Verilog-AGong Yuehong, Luo Min, Ma JianguoProblem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier … …Current Research in Nanotechnology, Vol. 2, Issue 2 · 3 Sep 2012 · 7,601 accessesView PDFCite
Research ArticleOpen accessIn the abstractSingle Core Hardware Module to Implement Boolean Function Classification TechniquesMohd. Marufuzzaman, Md. Mamun, Fazidah Hanim Hashim, Labonnah F. RahmanProblem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was … …American Journal of Applied Sciences, Vol. 8, Issue 11 · 7 Oct 2011 · 7,408 accessesView PDFCite
Research ArticleOpen accessIn the abstractHardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband ApplicationsMahmud Benhamid, Masuri B. OthmanProblem statement: Ultra Wide Band (UWB) technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 … …Journal of Mathematics and Statistics, Vol. 5, Issue 4 · 31 Dec 2009 · 7,515 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of Multi-Valued Quaternary Based Analog-to-Digital ConverterA.H.M. Zahirul Alam, Wahab Adetunji Lawal, Sheroz Khan, Muhammad Mahbubur RashidProblem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC) circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of … …American Journal of Applied Sciences, Vol. 6, Issue 8 · 31 Aug 2009 · 7,291 accessesView PDFCite
Research ArticleOpen accessIn the abstractUsing Combinational Circuits for Control PurposesMaher A. Nabulsi, Mohammed A.F. Al-HusainyProblem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of … …Journal of Computer Science, Vol. 5, Issue 7 · 31 Jul 2009 · 7,237 accessesView PDFCite
Research ArticleOpen accessIn the abstractFPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision GatingA. Senthilkumar, A. M. NatarajanWith the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition … …Journal of Computer Science, Vol. 4, Issue 2 · 28 Feb 2008 · 7,315 accessesView PDFCite
Research ArticleOpen accessIn the abstractDynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing ArchitecturesN. Ramadass, S. Natarajan, J. Raja Paul PerinbamEmerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic … …Journal of Computer Science, Vol. 3, Issue 10 · 31 Oct 2007 · 6,727 accessesView PDFCite
Research ArticleOpen accessIn the abstractDesign of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS TechnologySiva Kumar Palaniappan, Tun Zainal Azni ZulkifliThis paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes … …American Journal of Applied Sciences, Vol. 4, Issue 8 · 31 Aug 2007 · 7,164 accessesView PDFCite
Research ArticleOpen accessIn the abstractA New Efficient-Silicon Area MDAC SynapseZied Gafsi, Nejib Hassen, Mongia Mhiri, Kamel BesbesUsing the binary representation ΣiDi2i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named … …American Journal of Applied Sciences, Vol. 4, Issue 6 · 30 Jun 2007 · 7,158 accessesView PDFCite
Research ArticleOpen accessIn the abstractDigital Hardware Implementation of a Neural System Used for Nonlinear Adaptive PredictionHassène Faiedh, Chokri Souani, Kholdoun Torki, Kamel BesbesNeural networks have been widely used for many applications in digital communications. They are able to give solutions to complex problems due to their nonlinear processing and their learning and generalization. Neural networks are one of the key technologies for the communication domain and accordingly a special effort may be expected to be paid to real time hardware implementation issues. … …Journal of Computer Science, Vol. 2, Issue 4 · 30 Apr 2006 · 6,763 accessesView PDFCite