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Research ArticleOpen accessEvery word in the titleA Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous CircuitsD. Jayanthi, M. RajaramProblem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or … …Journal of Computer Science, Vol. 8, Issue 7 · 7 Jun 2012 · 7,084 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETERR. M. Bommi, S. Selvakumar RajaIn the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full … …Journal of Computer Science, Vol. 10, Issue 7 · 12 Feb 2014 · 6,674 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleHIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMSC. G. Ravichandran, S. VenkateshbabuThis study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing … …Journal of Computer Science, Vol. 10, Issue 5 · 30 Dec 2013 · 6,487 accessesView PDFCite
Research ArticleOpen accessEvery word in the titleOn-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDMRozita Teymourzadeh, Yazan Samir Algnabi, Nooshin Mahdavi, Masuri Bin OthmanProblem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 7,929 accessesView PDFCite
Research ArticleOpen accessIn the keywordsAREA EFFICIENT DISTRIBUTED ARITHMETIC DISCRETE COSINE TRANSFORM USING MODIFIED WALLACE TREE MULTIPLIERR. P. Meenaakshi Sundari, R. Anita, V. VenkateshwaranIn this study by using the modified Wallace tree multiplier, an error compensated adder tree is constructed in order to round off truncation errors and to obtain high through put discrete cosine transform design. Peak Signal to Noise Ratio (PSNR) is met efficiently since modified Wallace Tree method is an efficient, hardware implementable digital circuit that multiplies two integers resulting … …American Journal of Applied Sciences, Vol. 11, Issue 2 · 19 Dec 2013 · 7,335 accessesView PDFCite
Research ArticleOpen accessIn the keywordsGate Replacement Technique for Reducing Leakage Current in Wallace Tree MultiplierNaveen Raman, ThanushkodiLeakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace … …Journal of Computer Science, Vol. 9, Issue 2 · 30 Mar 2013 · 6,767 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,159 accessesView PDFCite
Research ArticleOpen accessIn the keywordsEfficient Reversible Montgomery Multiplier and Its Application to Hardware CryptographyNoor Muhammed Nayeem, Lafifa Jamal, Hafiz Md. Hasan BabuProblem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not … …Journal of Computer Science, Vol. 5, Issue 1 · 31 Jan 2009 · 7,858 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel High-Speed 54⨯54 bit MultiplierPouya Asadi, Keivan NaviA new 54⨯54-bit multiplier using high-speed carry-lookahead adder has been fabricated by CMOS technology. This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has … …American Journal of Applied Sciences, Vol. 4, Issue 9 · 30 Sep 2007 · 7,084 accessesView PDFCite
Research ArticleOpen accessIn the keywordsHARDWARE REALIZATION OF HIGH SPEED ELLIPTIC CURVE POINT MULTIPLICATION USING PRECOMPUTATION OVER GF(P)N. Shylashree, V. SridharTwo new theoretical approaches for the hardware realization of high speed elliptic curve point multiplication over a prime field (GF(p)) are presented. These hardware implementations use multiple units of elliptic curve point doublers, point adders and multiplexers. The modular hardware approach used here provides high speed and scalability. …Journal of Computer Science, Vol. 10, Issue 7 · 4 Feb 2014 · 6,614 accessesView PDFCite