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35 articles for “TI DSP”
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Research ArticleOpen accessIn the keywordsHardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA DevicesMuhammad H. RaisProblem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 1 · 31 Mar 2010 · 8,338 accessesView PDFCite
Research ArticleOpen accessIn the keywordsImplementation of Low-Memory Reference FFT on Digital Signal ProcessorYi-Pin Hsu, Shin-Yu LinProblem statement: In order to improve and implement Fast Fourier Transform (FFT), in general, an efficient parallel form in digital signal processor is necessary. The butterfly structure is an important role in FFT, because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even … …Journal of Computer Science, Vol. 4, Issue 7 · 31 Jul 2008 · 7,146 accessesView PDFCite
Research ArticleOpen accessIn the keywordsArtificial Neural Network Based Rotor Capacitive Reactance Control for Energy Efficient Wound Rotor Induction MotorK. Ranjith Kumar, S. Palaniswami, K. Siva KumarProblem statement: The Rotor reactance control by inclusion of external capacitance in the rotor circuit has been in recent research for improving the performances of Wound Rotor Induction Motor (WRIM). The rotor capacitive reactance is adjusted such that for any desired load torque the efficiency of the WRIM is maximized. The rotor external capacitance can be controlled using a dynamic … …Journal of Computer Science, Vol. 8, Issue 7 · 26 May 2012 · 7,166 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of Low- Power High-Speed Error Tolerant Shift and Add MultiplierK. N. Vijeyakumar, V. Sumathy, Sriram Komanduri, C. Chrisjin Gnana SujiProblem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder … …Journal of Computer Science, Vol. 7, Issue 12 · 18 Oct 2011 · 7,159 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Comparative Analysis of the Entropy and Transition Point Approach in Representing Index Terms of Literary TextHayati Abd Rahman, Shahrul Azman NoahProblem statement: Concept hierarchy is a hierarchically organized collection of domain concepts. It is particularly useful in many applications such as information retrieval, document browsing and document classification. Approach: One of the important tasks in construction of concept hierarchy is identification of suitable terms with appropriate size of domain vocabulary. Results: One way of achieving such a size is by … …Journal of Computer Science, Vol. 7, Issue 7 · 30 Jun 2011 · 6,678 accessesView PDFCite
Research ArticleOpen accessIn the keywordsSpartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay StudyMohammed H. Al MijalliProblem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be … …American Journal of Applied Sciences, Vol. 8, Issue 6 · 13 Jun 2011 · 6,431 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley MultipliersMuhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, Fahad K. Al-HusseinProblem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. … …American Journal of Engineering and Applied Sciences, Vol. 3, Issue 2 · 30 Jun 2010 · 8,129 accessesView PDFCite
Research ArticleOpen accessIn the keywordsA Novel Methodology for Designing Radix-2n Serial-Serial MultipliersAbdurazzag Sulaiman AlmiladiProblem statement: The fast growth and increase in complexity of digital and image processing systems necessitate the migration from ad hoc design methods to methodological ones. Methodologies will certainly ease the trade off selection for those systems and shortens the design time. To increase those gained values and expand the searching space more appropriate methodologies need to be developed. Approach: … …Journal of Computer Science, Vol. 6, Issue 4 · 30 Apr 2010 · 6,926 accessesView PDFCite
Research ArticleOpen accessIn the keywordsDesign of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS TechnologySiva Kumar Palaniappan, Tun Zainal Azni ZulkifliThis paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes … …American Journal of Applied Sciences, Vol. 4, Issue 8 · 31 Aug 2007 · 7,169 accessesView PDFCite
Research ArticleOpen accessIn the abstractAndroid Based Energy Aware Framework for Porting Legacy ApplicationsNaeem Zafar AzeemiTrend is growing towards using complex multimedia functions on smaller devices. In this study, we explore the effect of migrating legacy signal processing software applications algorithms from large form factor devices to the smaller one such as handheld mobile devices known as Energy Conscious Mobile Computing Systems (EConMCS). We concentrate on Source Code Volatility (SCV), including inherent algorithm complexity and … …American Journal of Applied Sciences, Vol. 11, Issue 12 · 3 Jan 2015 · 6,294 accessesView PDFCite